Hi,
I'm configuring the DMA for writing from internal RAM to EPI. While this transfers works one time, I fail to clear the interrupt, so that it is constantly re-triggered. I thought EPIIntErrorClear(EPI0_BASE,EPI_INT_ERR_DMAWRIC)
should do the job, but does not. To be clear: I checked, if any other Interrupt occurs, but it is only the EPI_INT_DMA_TX_DONE one.
Any Help is welcome,
regards
Micky
My Code is
uint16_t auData[512]={1,2,3}; uint16_t* pDst =(uint16_t*)0x80000400; ROM_uDMAChannelAttributeDisable(UDMA_CH21_EPI0TX, UDMA_ATTR_USEBURST); ROM_uDMAChannelAttributeEnable(UDMA_CH21_EPI0TX, UDMA_ATTR_USEBURST); ROM_uDMAChannelControlSet(UDMA_CH21_EPI0TX| UDMA_PRI_SELECT, UDMA_SIZE_16| UDMA_SRC_INC_16 | UDMA_DST_INC_NONE| UDMA_ARB_8); ROM_uDMAChannelTransferSet(UDMA_CH21_EPI0TX | UDMA_PRI_SELECT, UDMA_MODE_AUTO, auData,&pDst, 256); ROM_uDMAChannelAssign(UDMA_CH21_EPI0TX); ROM_uDMAIntClear(UDMA_CH21_EPI0TX); ROM_uDMAChannelEnable(UDMA_CH21_EPI0TX); ROM_uDMAChannelRequest(UDMA_CH21_EPI0TX); EPIDMATxCount(EPI0_BASE,256);
And the Interrupt service handler
void vfnEpi0Handler() { uint32_t uStatus; static uint32_t suEpiReady=0; uint32_t uInts = ROM_EPIIntStatus(EPI0_BASE,true); switch (uInts) { case EPI_INT_TXREQ: suEpiReady++; break; case EPI_INT_RXREQ: suEpiReady++; break; case EPI_INT_ERR: suEpiReady++; break; case EPI_INT_DMA_TX_DONE: suEpiReady++; EPIIntErrorClear(EPI0_BASE,EPI_INT_ERR_DMAWRIC); break; case EPI_INT_DMA_RX_DONE: suEpiReady++; break; default: break; } uStatus = ROM_uDMAChannelModeGet(UDMA_CH21_EPI0TX); if(uStatus == UDMA_MODE_STOP) { // DMA Ready suEpiReady++; } };