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Original question:

TMS570LC4357: Impact of the DMA on the CPU

TMS570LC4357: Arbitration to access CPU SRAM between masters

Mathieu Quenpt
Prodigy 210 points

Part Number: TMS570LC4357

According to this thread https://e2e.ti.com/support/microcontrollers/hercules/f/312/p/919525/3397342#3397342: "The CPU SRAM interconnect is designed such that an arbitration condition only exists if both the CPU and the DMA are accessing the same 64-bit address in the same cycle".

In which user manual can I find the statement that the arbitration between masters is only necessary in the same 64-bit address of the CPU SRAM?

Thank you!