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Original question:

TMS570LC4357: Impact of the DMA on the CPU

TMS570LC4357: simultaneous access by CPU and DMA to SRAM

Robert Finger
Mastermind 18223 points

Part Number: TMS570LC4357

Team,

In the following post it sounds like simultaneous accesses by CPU and DMA to SRAM are possible without any cycle penalty. As long as both accesses are to different 64 bit memory addresses:

https://e2e.ti.com/support/microcontrollers/hercules/f/312/p/919525/3397342#3397342

Is this understanding correct? And where in the TRM is this documented? A customer of mine is working on safety certification and they need to calculate worst case execution time. They need this officially documented in our docs. 

Thanks & best regards,
  Robert

  • 0
    TI__Mastermind 49120 points

    Hi Robert,

    The figure 4-1 in the TRM on page 266 shows a high-level representation of the main device interconnects. This shows a CPU interconnect subsystem which is responsible for arbitrating accesses to the "slaves" connected to this subsystem, including the L2 RAM.

    This chapter does not clearly specify this, but an arbitration condition only occurs when multiple bus masters are accessing the same 64-bit word. All other accesses are allowed to continue without any additional delay due to arbitration.