Team,
A customer has a question about servicing the SPI via DAM, copy data to SRAM:
...
The goal is to find out if DMA can transfer the data from the SPI modules to the SRAM quickly enough.
The processor operates at the following frequencies:
• GCLK 240MHz
• HCLK 120MHz
• VCLK 60MHz
• SPICLK 25MHz
The SPI is operated in slave mode at 25MHz, the MibSPI modules 1 to 4 are used in continuous mode, up to 1500 bytes per SPI and direction are transmitted. All data should be transferred in 500us.
That is, each SPI should have a DMA channel in receive and a DMA channel in the transmit direction.
The first DMA transfer is initiated by the software, after which the further transfers are to be started by channel chaining.
--> How can DMA transfer be configured here so that the data transfer between SPI Buffer and SRAM takes place as quickly as possible?
--> And how many clock cycles are needed for a data transfer?
--> Which clock does the DMA run with?
The following is our assumption for the sequence of a DMA transfer with a suspected number of clock cycles per step.
--> Are these assumptions correct? Or can you complete/improve the flow and timing information?
--> Are further parallelizations/optimizations possible?
• 1. DMA request by software
O DMA channels 0 and 1 read their primary control Package 6 cycles
O channel 0 and 1 write data to the working Images 3 cycles
O Arbitration may be necessary 1 cycle
O Wait States may be required ??? Cycles
O channel 0 and 1 perform DMA transfers Number of cycles = (Reads + Writes per element) X Number of elements in the block
• 2. DMA request for channels 2 and 3
• …
• For the next transfers for channels 0 and 1 Skip the step 'Share into working images'
--> Is a clock cycle required for a read or write operation (in the element)?
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Thanks & best regards,
Robert
