TMS570LS1224: Flash SECDED sector-wise disabling

Hi Luis,

The SEDED logic for main flash is inside the CPU, but the SEDED logic for EEPROM (Bank 7) inside the flash wrapper. Both SEDED logics can be disabled and re-enabled. But we can not disable the ECC protection just for only one flash sector.

Dear QJWang,

thanks for the swift response.

I have 3 further related questions:

• Flash Error Detection and Correction Sector Disable Registers FEDACSDIS and FEDACSDIS2 -- SPNU515C, page 298 and 317-- indicates that is possible to disable and re-enable sector-wise for EEPROM (Bank7), is my understanding correct?

• Please consider the following example using CRC module and SECDED enabled in Flash Bank0:
  • A memory area with 1M byte in Bank0 is to be checked in the background of CPU.
  • CRC is to be performed every 1K byte.
  • A single error caused by an energized particle occurs in a particular 1K byte data pattern at the time its signature is to be calculated
  • Is the single error corrected by Flash SECDED before CRC is calculated?
  • What is the result of the comparison of the data pattern calculated CRC with the pre-recorded CRC value?

Thank you for the time and support.

Best regards,

Luis

Hi Luis,

1. You are correct. You can disable the SECDED function for 4 sectors in Bank 7. 

2. The data with 1-bit ECC error should be corrected when CPU reads the data for CRC calculation. But the corrected data is not written back to flash. 

Hello, QJ Wang

Thanks a lot for the swift response, it was very helpful.

I have further questions, thanks for the time.

Context:

I am working on a project that focus on developing a MCU boot-sofware via CAN.

The boot-SW should provide the user with the funtionality of selecting for operation (it will be excuted) one of two pre-stored application-SW images.

E.g., application-SW image-1 stored in flash bank 0, sectors 8-11 and image-2 in fash bank 0 sectors 12-15.

Moreover, the boot-SW also should provide the capability to reload (support transfer via CAN bus and program into the Flash) a user selected application-SW image.  

Questions

1. In case the user selects for operation using e.g., image-1, and some time later an uncorrectable error is detected by SECDED in the memory region were the image-1 is stored: does it generate a CPU abort?
2. In case the user selects for operation using e.g., image-1, and some time later an uncorrectable error is detected by SECDED in the memory region were the image-2 is stored: does it generate a CPU abort?
3. In case a new application-sw image is to be reloaded, in order to make sure SECDED will continue working after reload, the new and correct associated  values -- generated by now ECC -- of the ECC must also be transfered along with the application-sw image and then, programed into the Flash after the image is programed and before SECDED is re-enabled. Is my understanding correct? 
4. According to SPNU515c "The Cortex-R4 CPU may generate speculative fetches to any location within the ATCM memory space.", what are the conditions that must be satisfied to trigger a fetch?

Again, thanks a lot for your time.

Best regards,

Luis

Hello,

1 & 2: Yes. It will generate a group 3 channel 7 ESM error, which toggles the nERROR pin. It will generate CPU abort too.

3. The F021 flash API is able to calculate ECC and program ECC to ECC space while programming data to main flash. 

     Fapi_issueProgrammingCommand((uint32_t *)dst, (uint8_t *)src, (uint32_t) bytes, 0, 0, Fapi_AutoEccGeneration);

     Fapi_AutoGeneration – This will program the supplied data portion in Flash along with automatically generated ECC. ECC is calculated on 64-bit aligned addresses up to the data width of the bank. Data not supplied is treated as 0xFF. For example, on a device with a 144-bit wide bank width, if data is written only to bytes 0x0-0x7 (or 0x8-0xF), then the ECC will only be calculated for those 64 bits. If the data supplied crosses a 64-bit boundary, ECC will be calculated for both 64-bit words. For example, on a device with a 144-bit wide bank width, data is written to bytes 0x4 - 0xB, the 2 bytes of ECC data will be calculated. The data restrictions for Fapi_DataOnly also exist for this option.

     Please refer to the F021 flash API reference guide: SPNU501G.pdf

4. The CPU tries to make speculative fetches from the flash and RAM regions in order to minimize the impact of higher-latency memory accesses. If this access happens to fetch from a location that does not have the correct corresponding ECC programmed, this would generate an ECC error. There would be no abort generated if the CPU does not actually execute this instruction that was fetched speculatively. 

You need to fill any unused flash memory and then program the corresponding ECC codes as well.

Dear QJ Wang,

again thanks for the time, one final question:

Is it possible to disable (and re-enable) the DED part of the SECDED function for both, Flash bank 0 and bank 7 (and leave it enabled in RAM)?

In other words, is is possble to only enable the SEC part of the SECDED function?

Best regards,

Luis

Hi Luis,

No. But you can block Bank 7 uncorrectable ECC error (ESM 1.36) from generating interrupt or asserting nERROR pin.  

Dear QJ Wang,

thanks again for the support.

According to ARM and TI references for the cortex R4F, when a 2-bit ECC error is detected on a TMC read e.g., the Flash bank0, a synchronous data abort takes place and subsequently it is handled by the default data abort exception handler routine.

Is it possible to the user to extended the default handler routine?

If so, is it possible to extend it in such a way that it reads the Data Fault Address Register and checks if the memory address falls within a predefine memory region and, if so the processor resumes operation; otherwise forces the processor to loop indefinitely(*)?

(*) Here the idea in the system under design is to halt the generation of a MCU internally generated watchdog-feed-signal for at least a predefined duration that causes the trigger of an MCU external watchdog circuitry that will perform a power cycle of the MCU.  

Best regards,

Luis

Hello Luis,

All the uncorrectable error except for the error generated by selftest should not be ignored. The nERROR pin is asserted when 2-bit ECC error is detected regardless of how you handle the error in abort.asm.