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Original question:

TMS570LC4357: eQEP IRQ stops being called when using a maskable IRQ

TMS570LC4357: Using the nested IRQ

Frederic Desy
Prodigy 240 points
Part Number: TMS570LC4357

Hello,

when using the nested interrupts, as described in the application report SNA219, is there any considerations to have regarding the usage of the cache, on the TMS570LC4357?

I am asking this question because we are experiencing scenarios with the EMAC and the eQEP where the interrupts associated are not being called after a certain period of time, even if the IRQ pending flag has been set. We described this issue in the previous tickets:

https://e2e.ti.com/support/microcontrollers/hercules/f/312/p/953623/3529461

https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/965417

Thank you for your assistance.

Best regards,

Frederic.

  • 0
    TI__Guru**** 196776 points

    Hello Frederic,

    The memory for peripheral registers and VIM RAM is configured as either device mode or strongly-ordered mode. TMS570LC43x only supports L1 cache, so the cache property is only applicable for normal non-shared memories.

    Enabling/disabling cache in this device doesn't affect the irq-dispatch mentioned in the application note: SNA219

    The ARM Cortex-R4/R5 microcontroller does not support interrupt nesting in hardware. The irq-patch mentioned in this example uses the legacy index interrupt rather than the vectored interrupt. As you knew that the vectored interrupt offers high-performance, low-latency interrupt handling.

  • 0 in reply to QJ Wang
    Prodigy 240 points

    Hello QJ,

    thank you for your reply. It makes sense.

    But for the issue raised in the 2 previous tickets, how would a non-maskable IRQ stopped being serviced (even with its pending flag set) while the maskable IRQ (only one interrupt uses the patch of SPNA219 in our system) continues to be called?

    Did you try the sample code we sent?

    Kind regards,

    Frederic.

  • 0 in reply to Frederic Desy
    TI__Guru**** 196776 points

    I will run the test later today.

  • +1 in reply to QJ Wang
    TI__Guru**** 196776 points

    Used another thread for this SW nested interrupt question.