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Hi experts,
In Chapter 7.102 the Primary SRAM Data ECC is described. Out intention is to bring our system into a safe state once an error is detected. This includes the detection of (correctable) single bit errors.
If my understanding is correct, this is done by configuring the EPC SERRENA bit accordingly.
What is confusing to me, is that Chapter 7.102 states the following:
"Detected uncorrectable errors result in a ESM error. In the case of a single
bit error the CPU exports the error detection events to the EPC module, in case of a double bit error the
CPU exports the error event to the ESM module. The Cortex-R5F PMU must first be set to export events
to an external monitor."
(Q1) I know that the PMU can be used to count events, but I do not understand, why and how the PMU must be set to export events to an external monitor?
Because of our goal to bring the system into a safe state when an error occurs we do not plan to use the PMU to count such events.
(Q2) Does this mean that turning the PMU off, would interfere with our ability to detect (correctable) single bit errors?
Thank you and best regards,
Max
Hello Max,
When the CPU detects an ECC error on a read from flash/sram memory, it signals this on a dedicated “Event” bus. This event bus signaling is not enabled by default and must be enabled by the application. Writing 0x1 to 4th bit of PMU PMCR register is to to enable the CPU event signaling.
The function _coreEnableEventBusExport_() defined in HAL generated code HL_sys_core.asm will enable this feature.
