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TMS570LC4357: Why must the PMU set to export events to external monitor to enable single bit error detection in EPC?

Max Wittekind
Expert 1875 points
Part Number: TMS570LC4357


Hi experts,

In Chapter 7.102 the Primary SRAM Data ECC is described. Out intention is to bring our system into a safe state once an error is detected. This includes the detection of (correctable) single bit errors.
If my understanding is correct, this is done by configuring the EPC SERRENA bit accordingly.

What is confusing to me, is that Chapter 7.102 states the following:

"Detected uncorrectable errors result in a ESM error. In the case of a single
bit error the CPU exports the error detection events to the EPC module, in case of a double bit error the
CPU exports the error event to the ESM module. The Cortex-R5F PMU must first be set to export events
to an external monitor."

(Q1) I know that the PMU can be used to count events, but I do not understand, why and how the PMU must be set to export events to an external monitor?

Because of our goal to bring the system into a safe state when an error occurs we do not plan to use the PMU to count such events.

(Q2) Does this mean that turning the PMU off, would interfere with our ability to detect (correctable) single bit errors?

Thank you and best regards,
Max

 

  • 0
    TI__Guru**** 198766 points

    Hello Max,

    When the CPU detects an ECC error on a read from flash/sram memory, it signals this on a dedicated “Event” bus. This event bus signaling is not enabled by default and must be enabled by the application. Writing 0x1 to 4th bit of PMU PMCR register is to to enable the CPU event signaling.

    The function _coreEnableEventBusExport_() defined in HAL generated code HL_sys_core.asm will enable this feature.

  • 0 in reply to QJ Wang
    Expert 1875 points

    Hello QJ,

    Thank you for the quick answer.

    So writing 0x1 to 4th bit of PMU PMCR register and then setting the EPC SERRENA bit to Ah will enable the signalling of single bit errors to the ESM?

    Thank you and best regards,
    Max

  • 0 in reply to Max Wittekind
    TI__Guru**** 198766 points

    Hi Max,

    Yes. After those two bits are set, EPC will generate SERR_EVENT and ESM 1.4 will be set if there is a correctable ECC error and CAM has an empty entry or is full. 

    The main goal of EPC is to enable the system to tolerate a certain amount of ECC correctable errors on the same address repeatedly in the memory system with minimal runtime overhead.

    1. EPC captures the address of correctable ECC error, and write it to CAM (32-entry memory in EPC)

    2. When a correctable error occurs, 

         a. If the error address is already in the CAM, the error is discard. ESM 1.4 is not set

         b. If the error address is not in the CAM, and the CAM is not full, add this error address into the CAM, and raise the error flag to ESM 1.4.

         c. If the error address is not in CAM, and the CAM is full, the ESM1.4 is also set.