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Original question:

TMS570LC4357: Interfacing on EMIF with asynchronous 2x8bit MRAM (MR4A08BUYS45)

RM57L843: EMIF interfacing four MRAM chips

Wojciech B??dzi?ski
Prodigy 20 points
Part Number: RM57L843

Dear TI' support,

I need to connect 12M size of MRAM memory to RM57 processor.
MRAM is MR5A16A so it's 16b and I think of connecting four of them to EMIF interface.

since the address range of MR5A16A is [20:0] then my idea is to use AND gate with ADDR[21] and nCS signal to select particular chip.
so one AND gate, two MR5A16A chips could serve on single nCS.
eventually I'm going to use nCS2 and nCS3 to connect four MRAM chips, and have nCS3 left for connecting flash memory.

please kindly check if my idea has no issues other than impossibility to use 8bit pointer.

similar topic I found on TMS570, but designer had no intention to use so big memory space.

https://e2e.ti.com/support/microcontrollers/hercules/f/hercules-safety-microcontrollers-forum/759039/tms570lc4357-interfacing-on-emif-with-asynchronous-2x8bit-mram-mr4a08buys45

below you can find electrical connection schematic diagram of my idea.


thank you in advance,
Wojciech

  • 0
    TI__Guru**** 196836 points

    Your idea works. The memory range for two memory chips may not be from 0x6000_0000 to 6200_0000, and 0x6200_0000 to 0x6400_0000.

  • 0 in reply to QJ Wang
    Prodigy 20 points

    Thank you QJ,
    I appreciate your support, went thru E2E forum reading your comments reg. Hercules processors
    hoping that exactly You will answer my question :-)

    regarding your remark about address ranges appropriate for proposed circuit you are right. Properly calculated ranges are:
    for nCS2 0x6000 0000 - 0x600F FFFF(1stchip); 0x6010 0000 - 0x601F FFFF(2nd chip)

    the only one thing I don't get: how EMIF_BA[0] signal works (accessing asynchronous memory): as LSB (EMIF_A[0]) or as MSB (EMIF_A[22])?
    either way it seems to me that I have possibility of further expansion my memory bank by factor of 2.

    Thank you again,
    have a good day,
    Wojciech Błędziński

  • +1 in reply to Wojciech B??dzi?ski
    TI__Guru**** 196836 points

    The TRM says that BA[0] can be used as the upper address (A[22]). This is not correct. This device is designed for functional safety application, only 16MB (A[21:0]) is implemented for each CSx. Accessing the memory location beyond this range will generate abort. 

    So BA[0] can not be used as A[22].