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TMS320F28388D: SCI Bus architecture

B M Mohan
Expert 1720 points
Part Number: TMS320F28388D

Hello Experts,

I have a question on Peripheral Bus architecture.

We have four SCI modules, lets say A is assigned to Core 1 and B is assigned to Core and lets assume both cores initiated the  communication at the same exact moment.

Now, who will get the bus priority? Core 1 or Core 1? or Both?

Do you have any documents which talks about bus architecture for peripherals, where this interference scenario can be visualized.

Regards,

Mohan

  • 0
    TI__Mastermind 19795 points

    Hi Mohan,

    Thanks for your question! From the standpoint of the SCI modules themselves, if you are using interrupts, it will always be the SCI module with the highest interrupt priority that will communicate first. Interrupts prioritization determines the order of interrupt calls (can be changed via software prioritization with some effort).

    Let me know if you are not using interrupts, as that will require involvement from our dual-core experts.

    Regards,

    Vince

  • 0 in reply to Vince
    Expert 1720 points

    Hi Vince,

    Thank you for the response

    However, I am specifically looking for peripheral interference in the controller.

    Configuration in my applications are:

    1. ADC interrupt - Highest

    2. SCI interrupt in both cores

    3. Timer 0 Interrupt in both cores.

    My question is in such a way that, both cores will be accessing the peripheral assigned for it in the same Peripheral Frame. One more example would be usage of two different PWM modules used by two cores. The same question comes again, if both cores try to update the compare values and change the PWM output at the same time. Which core would get the preference or can it execute and update parallelly at the same time.

    This information and documentation is critical for my application, as this will be presented to FAA for certification purpose.

    Regards,

    Mohan

  • 0 in reply to B M Mohan
    TI__Mastermind 19795 points

    Hi Mohan,

    I have reached out to our dual-core expert for assistance with your question.

    Regards,

    Vince

  • 0 in reply to Vince
    TI__Guru** 113755 points

    Mohan,

    B M Mohan said:
    My question is in such a way that, both cores will be accessing the peripheral assigned for it in the same Peripheral Frame.

    Each CPU subsystem have their own peripheral frame so there is no conflict when CPU are accessing peripherals on their own peripheral frames.

    B M Mohan said:
    One more example would be usage of two different PWM modules used by two cores. The same question comes again, if both cores try to update the compare values and change the PWM output at the same time. Which core would get the preference or can it execute and update parallelly at the same time.

    As mentioned in last question, both cores will be able to update their own PWM in parallel at same time.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Expert 1720 points

    Thank you, Vivek,

    how about bus contention, is there any documentation where I can refer to this?

    Regards,

    Mohan

  • 0 in reply to B M Mohan
    TI__Guru** 113755 points

    Mohan,

    What do you mean by bus contention? CPU1/CPU2 access are controlled by mux so at a time only one CPU will have access to the peripherals.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Expert 1720 points

    Can I understand, that each peripheral has independent bus lines for it?

    For example, In SCI, I give SCI A to Core 1 and SCI B to Core, then SCIA has it's own bus line connected via mux and SCIB has its own bus line connected to another mux for CPU 2.

    as per the TRM, in section  11.6 CPU and CLA Arbitration, an example is provided for CPU, CLA, and DMA peripheral contention. I do not see any such example for CPU 1 and CPU2 peripheral contention. If it does not happen as per your previous explanation, how the bus is organized.

    could you please refer me to any documentation.

    Regards,

    Mohan

  • 0 in reply to B M Mohan
    TI__Guru 55700 points

    Mohan,

    We don't have separate document on this topic. I believe Vivek answer to your question is clear. When peripherals are assigned to different CPUs they don't share same peripheral frame. So there won't be any contention.

    Regards,

    Manoj