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SOC trigger from ePWM disappears

Glib Dovgych
Prodigy 160 points
Other Parts Discussed in Thread: TMS320F28035

Hello everyone!

 

I'm using ePWM SOC trigger to start ADC convertion on CTR = PRD. I'm using TMS320F28035.

    EPwm2Regs.ETSEL.bit.SOCAEN    = 1;    // Enable SOC on A group
    EPwm2Regs.ETSEL.bit.SOCASEL  = 4;    // Select SOC from CTR=PRD
    EPwm2Regs.ETPS.bit.SOCAPRD   = 1;    // Generate pulse on 1st event

It used to work well, but now sometimes PWM counter stops running and as a result it stops triggering SOC. I tried to find out the reason and first I thought that it happens because of the SWFSYNC impulse, 'cause according to the algorithm I use SWFSYNC either in Timer0 isr or in external interrupt isr.  Which of those isr will generate the SWFSYNC depends on external signal switch. I have a signal that goes to the comparator and output of the comparator is connected to the external interrupt input pin. So, if I have a signal on the comparator greater than the reference from internal DAC, once during the signal period I have an external interrupt and this isr generates SWFSYNC. If this interrupt doesn't fire for some defined period of time, I have a Timer0 interrupt, which also calls  SWFSYNC. So, when I'm switching ON or OFF the signal on the comparator input, the ePWM module stops working. I use SWFSYNC the same way in both isr so it doesn't explain the problem. This signal switching can be followed by some EMI. But as I know the PWM counter can be stopped only by changing the value of CTRMODE register, which is EALLOW protected...

 

Can anyone give any advice?

  • 0
    TI__Mastermind 43730 points

    What mode are you operating your PWM in? Up down count or only up count?

    I can see if your PWM sync is such that it never lets the counter go to the PRD value it would never generate the SOC. However there is no reason for the counter to stop!

    How are you verifying that the counter is stopped?

  • 0 in reply to Manish Bhardwaj
    Prodigy 160 points

    Thanks for your answer, Manish!

    I'm using up-count mode.

    Sync is being generated once in 500 PWM periods, so it couldn't prevent PWM counter from reaching PRD.

    I see that there's zero signal on the PWM output, although PWM output should go HIGH on CTR=0 and LOW on CTR = CMPA (and CMP is not equal to 0). And also I see that no SOC pulse is generated anymore. That's why I think that the counter stops.

    I've looked through the silicon errata but didn't find any problem that looks like mine...

  • 0 in reply to Glib Dovgych
    Expert 2355 points

    Glib,

    Are you able to post the full initialization code for both your ePWM and ADC?

    Tim

  • 0 in reply to Tim King61612
    Prodigy 160 points

    My PWM config looks like this:

        EALLOW;

        EPwm2Regs.TBCTL.all         = 0;                 // all prescalers are 1
        EPwm2Regs.TBCTL.bit.CTRMODE = 0;    // count-up mode
        EPwm2Regs.TBPRD             = 2400;          // Init value of PWM period
        EPwm2Regs.TBCTL.bit.SYNCOSEL= 0;   // Select SyncOut to EPWM2SYNC
        EPwm2Regs.TBCTL.bit.PHSEN     = 1;      // Enable syncronisation on SWFSYNC
        EPwm2Regs.TBPHS.half.TBPHS     = 0;    // Start count from 0 when syncronized

        EPwm2Regs.ETSEL.bit.SOCAEN    = 1;     // Enable SOC on A group
        EPwm2Regs.ETSEL.bit.SOCASEL    = 4;   // Select SOC from CTR=PRD (6 for CMPB up count)
        EPwm2Regs.ETPS.bit.SOCAPRD     = 1;   // Generate pulse on 1st event

        EPwm2Regs.AQCTLA.all         = 0;              // default parameters
        EPwm2Regs.AQCTLA.bit.ZRO     = 2;         // set ePWM2A on ZERO
        EPwm2Regs.AQCTLA.bit.CAU     = 1;         // clear ePWM2A on CMPA up

        EPwm2Regs.CMPCTL.bit.LOADAMODE = 0;        // Load CMPA on CTR = ZERO
        EPwm2Regs.CMPA.half.CMPA     = period/2;        // 50% duty cycle first
        EPwm2Regs.CMPB                = 0;                             // Load period into CMPB           

        EPwm2Regs.DBRED                =10;    // Rising edge delay
        EPwm2Regs.DBFED                =10;    // Falling edge delay
        EPwm2Regs.DBCTL.all         = 0;    // Default config
        EPwm2Regs.DBCTL.bit.POLSEL    = 2;    // Active HIGH complementary (ePWM2B is inverted) 
        EPwm2Regs.DBCTL.bit.OUT_MODE= 3;    // Dead-band is fully enabled

        EPwm2Regs.HRCNFG.all             = 0;    // Set default values
        EPwm2Regs.HRCNFG.bit.EDGMODE    = 1;    // MEP control on rising edge
        EPwm2Regs.HRCNFG.bit.CTLMODE    = 0;    // MEP is controlled by CMP or PRD
        EPwm2Regs.HRCNFG.bit.HRLOAD     = 0;    // Load CMPAHR on CTR = ZERO
        EPwm2Regs.HRCNFG.bit.AUTOCONV    = 0;    // non-automatic HRMSTEP scaling is enabled
        EDIS;

     

    And my ADC config is:

        EALLOW;

        EALLOW;
        AdcRegs.ADCCTL1.bit.INTPULSEPOS    = 1;          //ADCINT1 trips after AdcResults latch
        AdcRegs.ADCSAMPLEMODE.bit.SIMULEN0 = 1;    //Enable simultenious sampling

        AdcRegs.INTSEL1N2.bit.INT1E     = 1;         //Enabled ADCINT1
        AdcRegs.INTSEL1N2.bit.INT1CONT  = 0;   //Disable ADCINT1 Continuous mode
        AdcRegs.INTSEL1N2.bit.INT1SEL    = 1;     // setup EOC1 to trigger ADCINT1 to fire

        AdcRegs.ADCSOC0CTL.bit.CHSEL     = 0;     //set SOC0 channel select to ADCINA0
        AdcRegs.ADCSOC0CTL.bit.TRIGSEL     = 7;  //set SOC0 start trigger on EPWM2A, due to round-robin SOC0 converts first
        AdcRegs.ADCSOC0CTL.bit.ACQPS     = 6;     //set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)

        AdcRegs.ADCSOC1CTL.bit.CHSEL     = 8;     //set SOC1 channel select to ADCINB0
        AdcRegs.ADCSOC1CTL.bit.TRIGSEL     = 7;  //set SOC1 start trigger on EPWM2A, due to round-robin SOC0 converts first
        AdcRegs.ADCSOC1CTL.bit.ACQPS     = 6;     //set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)

        AdcRegs.ADCSOC2CTL.bit.CHSEL     = 5;     //set SOC2 channel select to ADCINA5
        AdcRegs.ADCSOC2CTL.bit.TRIGSEL     = 7;  //set SOC2 start trigger on EPWM2A, due to round-robin SOC2 converts first then SOC3
        AdcRegs.ADCSOC2CTL.bit.ACQPS     = 6;     //set SOC2 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)

        AdcRegs.ADCSOC3CTL.bit.CHSEL    = 13;     //set SOC3 channel select to ADCINB5
        AdcRegs.ADCSOC3CTL.bit.TRIGSEL     = 7;   //set SOC2 start trigger on EPWM2A, due to round-robin SOC2 converts first then SOC3
        AdcRegs.ADCSOC3CTL.bit.ACQPS     = 6;      //set SOC2 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
       
        EDIS;