TMS320F280049: Clarify the mask for nesting ISR in the technical doc

Dear Champs,

I am asking this for our customer.

We have nesting ISR examples online in

https://software-dl.ti.com/C2000/docs/c28x_interrupt_nesting/html/index.html

Or in offline c2000ware

C:\TI\c2000\C2000Ware_3_04_00_00\docs\c28x_interrupt_nesting

There is an example below,

interrupt void EPWM1_TZINT_ISR(void) // EPWM1 Trip Zone
{
        uint16_t TempPIEIER;
        TempPIEIER = PieCtrlRegs.PIEIER2.all;
        IER |= M_INT2;
        IER &= MINT2;                         // Set "global" priority
        PieCtrlRegs.PIEIER2.all &= MG21;      // Set "group" priority
        PieCtrlRegs.PIEACK.all = 0xFFFF;      // Enable PIE interrupts
        asm("       NOP");                    // Wait one cycle
        EINT;                                 // Clear INTM to enable interrupts
        //
        // Insert ISR Code here.......
        // for now just insert a delay
        //
        for(i = 1; i <= 10; i++) {}
        //
        // Restore registers saved:
        //
        DINT;
        PieCtrlRegs.PIEIER2.all = TempPIEIER;
}

But in legacy device like F2837xS,

C:\TI\c2000\C2000Ware_3_04_00_00\device_support\f2837xs\examples\cpu1\sw_prioritized_interrupts\cpu01\SWPrioritizedDefaultIsr.c

It shows,

__interrupt void EPWM1_TZ_ISR(void) // ePWM1 Trip Zone
{
// Set interrupt priority:
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all;
IER |= M_INT2;
IER &= MINT2; // Set "global" priority
PieCtrlRegs.PIEIER2.all &= MG2_1; // Set "group" priority
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
__asm(" NOP");
EINT;

//
// Insert ISR Code here.......
//
for(i = 1; i <= 10; i++) {}

//
// Restore registers saved:
//
DINT;
PieCtrlRegs.PIEIER2.all = TempPIEIER;

//Add ISR to Trace
ISRTrace[ISRTraceIndex] = 0x0021;
ISRTraceIndex++;
}

One shows MG21 and the other shows MG2_1, and they are different.

Which one is correct?

Wayne Huang