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Hi TI experts,
I try to use three ISR to perform in our project.
ADCAISR will be performed every 100us.
Timer1 will transmit data to the external device and be perform every 500us.
SCIARXISR will receive data from the external device.
I refer to the example code and TI wiki(https://processors.wiki.ti.com/index.php/Interrupt_Nesting_on_C28x) to build the software prioritization.
When interrupt start, three interrupt are working fine, but SCIRXISR will not be triggered after 5 sec.
Does any wrong in our setting?
The following figure is the abnormal condition in SCIRXISR.
CH1: ADCAISR-100us
CH2:SCIARXISR
CH3:Timer1ISR-500us
CH4:SCIA RX signal
related code as following:
#define INT1PL 1 // Global Priority for Group1 Interrupts
#define INT2PL 0 // Global Priority for Group2 Interrupts
#define INT3PL 0 // Global Priority for Group3 Interrupts
#define INT4PL 0 // Global Priority for Group4 Interrupts
#define INT5PL 0 // Global Priority for Group5 Interrupts
#define INT6PL 0 // Global Priority for Group6 Interrupts
#define INT7PL 0 // Global Priority for Group7 Interrupts
#define INT8PL 0 // Global Priority for Group8 Interrupts
#define INT9PL 2 // Global Priority for Group9 Interrupts
#define INT10PL 0 // Global Priority for Group10 Interrupts
#define INT11PL 0 // Global Priority for Group11 Interrupts
#define INT12PL 0 // Global Priority for Group12 Interrupts
#define INT13PL 3 // Global Priority for INT13 (TINT1)
#define INT14PL 0 // Global Priority for INT14 (TINT2)
#define INT15PL 0 // Global Priority for DATALOG
#define INT16PL 0 // Global Priority for RTOSINT
__interrupt void adcA1ISR(void)
{
GPIO_writePin(6,1);
//
// Save IER register on stack
//
volatile uint16_t tempPIEIER = HWREGH(PIECTRL_BASE + PIE_O_IER1);
//
// Set the global and group priority to allow CPU interrupts
// with higher priority
//
IER |= M_INT1;
IER &= MINT1;
HWREGH(PIECTRL_BASE + PIE_O_IER1) &= MG1_1;
//
// Enable Interrupts
//
Interrupt_clearACKGroup(0xFFFFU);
__asm(" NOP");
EINT;
//
// Insert ISR code here
//
if(true == ADC_getInterruptOverflowStatus(ADCA_BASE, ADC_INT_NUMBER1))
{
ADC_clearInterruptOverflowStatus(ADCA_BASE, ADC_INT_NUMBER1);
}
ADC_clearInterruptStatus(ADCA_BASE, ADC_INT_NUMBER1);
//
// Disable interrupts and restore registers saved:
//
DINT;
HWREGH(PIECTRL_BASE + PIE_O_IER1) = tempPIEIER;
GPIO_writePin(6,0);
}
__interrupt void cpuTimer1ISR(void)
{
GPIO_writePin(12,1);
//
// Set the global priority to allow CPU interrupts with higher priority
//
IER &= MINT13;
EINT;
//
// Insert ISR code here
//
SCI_Tx_Data();
cpuTimer1IntCount++;
//
// Disable Interrupts
//
DINT;
GPIO_writePin(12,0);
}
__interrupt void sciaRxISR(void)
{
GPIO_writePin(8,1);
//
// Save IER register on stack
//
volatile uint16_t tempPIEIER = HWREGH(PIECTRL_BASE + PIE_O_IER9);
//
// Set the global and group priority to allow CPU interrupts
// with higher priority
//
IER |= M_INT9;
IER &= MINT9;
HWREGH(PIECTRL_BASE + PIE_O_IER9) &= MG9_1;
//
// Enable Interrupts
//
Interrupt_clearACKGroup(0xFFFFU);
__asm(" NOP");
EINT;
//
// Insert ISR code here
//
SCI_Rx_Data_Handle();
SCI_resetRxFIFO(SCIA_BASE);
SCI_clearInterruptStatus(SCIA_BASE, SCI_INT_RXFF);
//
// Disable interrupts and restore registers saved:
//
DINT;
HWREGH(PIECTRL_BASE + PIE_O_IER9) = tempPIEIER;
GPIO_writePin(8,0);
}
