• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 82 subscribers
  • Views 553 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F280049: Nesting interrupt

Jack Tan80
Mastermind 7140 points
Part Number: TMS320F280049
Other Parts Discussed in Thread: C2000WARE

Dear C2000 expert,

I see the documentation has described the nesting inerrupt, file:///C:/ti/c2000/C2000Ware_3_04_00_00/docs/c28x_interrupt_nesting/html/index.html.

My application is pretty simple, only 2 interrupts are used, timer0 and epwm1 period interrupt in my code.

And I'd like the timer0's interrupt can be nested, and set epwm1's period interrupt is the highest priority. 

I just add below code in timer0ISR, and didn't modify IER and PIEIER in timer0ISR,  can you please help me know if any risk here?

__interrupt void cpuTimer0ISR(void)
{

    GpioDataRegs.GPBSET.bit.GPIO34 = 1;

    /* Enable Interrupts */
    Interrupt_clearACKGroup(0xFFFFU);
    __asm("  NOP");
    EINT;
    
    /* My isr code begin here */
    
    /* ... */
    /* ... */
    /* ... */
    
    /* My isr code end here */
    
    DINT;

    GpioDataRegs.GPBCLEAR.bit.GPIO34 = 1;

}

Regards,

Jack

  • 0
    TI__Genius 11645 points

    Jack,

    You can find a very similar example in the below location,

    C2000Ware_3_04_00_00\driverlib\f28004x\examples\interrupt\interrupt_ex2_sw_prioritization.c

    Copied the snippet below for your reference as well.

    __interrupt void cpuTimer0ISR(void)
{

// Save IER register on stack
volatile uint16_t tempPIEIER = HWREGH(PIECTRL_BASE + PIE_O_IER1);

// Set the global and group priority to allow CPU interrupts with higher priority
IER |= M_INT1;
IER &= MINT1;
HWREGH(PIECTRL_BASE + PIE_O_IER1) &= MG1_7;

// Enable Interrupts
Interrupt_clearACKGroup(0xFFFFU);
__asm(" NOP");
EINT;


// Insert ISR code here
...
...
...


// Disable interrupts and restore registers saved:
DINT;
HWREGH(PIECTRL_BASE + PIE_O_IER1) = tempPIEIER;

}

  • 0 in reply to KARTHIKEYAN RAJAMANICKAM
    Mastermind 7140 points

    Karthikeyan,

    Thanks for supporting here. 

    I see the example, but the example has lots of #define and #if to get desired IER and PIEIERx value. And there are only 2 interrupts are used in my case, this is pretty simple. So I don't plan to add the sw_prioritized_isr_levels.h.

    As my understanding, the example support nesting interrupt for the same group. For example, INT1.1 and INT1.2 can be set to nested interrupt.

    In my example, timer0 and epwm1 period interrupt are used, and timer0 is INT1.7, epwm1's period interrupt is INT3.1. 

    They are not belongs to the same group, so it's unneccessary to modify PIEIER1 register in timer0 isr, and when timer0's isr is excuted, the IER.1 will be cleared, IER.3 is still set. In this point, it's unneccessary to modify both IER and PIEIER1 register in my case, can you please help to evaluate if my understand is correct?

    Regards,

    Jack

  • 0 in reply to Jack Tan80
    Mastermind 7140 points

    Dear Karthik,

    May I have further comments from yours?

    Regards,

    Jack

  • +1 in reply to Jack Tan80
    TI__Genius 11645 points

    Hello Jack,

    If the other interrupt is from a different group(and not other interrupts are involved) then most part of the other code is not needed.

    Mostly what you have should suffice.