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TMS320F280049: Interrupt nesting configuration of TMS320F280049

yun long
Intellectual 260 points
Part Number: TMS320F280049

Tool/software:

Hello, experts
 
          I have  a question about C2000 interrupt nesting.  There are 3 ISRs: EPWM_ISR, TIMER0_ISR and SCI_RXB_ISR in my application. EPWM_ISR is main for generating PWM wave, and its frequency is 50kHz. TIMER0_ISR is main for background task, its interrupt frequency is 5kHz, SCI_RXB_ISR is for communication with GUI. I have read the paper of C28x_interrupt nesting, and TRM of TMS320f280049 of system interrupt.
I found SCI_RXB_ISR is disturbed by TIMER0 interrupt and EPWM1 interrupt. So I added interrupt in TIMER0 interrupt and EPWM1 interrupt. The code is as follow.
SCI_ISR:
SCI_Code
TIMER0_ISR
EPWM1_ISR code:
My question is that:
1. In interrupt nesting,  whether different PIE groups do not require control over the PIE registers; only the IER register needs to be modified. Even IER may not need in different PIE group. Only EINT can enable the interrupt nesting, if I don't want to mask other two interrupts. For example, in TIMER0_ISR:
Uint16 TempIER;
TempIER = IER;
//IER |= M_INT9;//; // Set global priority by adjusting IER
IER &= M_INT9;
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
asm(" NOP"); // Wait one cycle
EINT;
1.Whether I could delete the IER code and PIE code, and only leave EINT， which will result in SCI_ISR and EPWM_ISR interrupt nesting in the TIME0_ISR. Using IER can mask and enable the interrupt which is desired. 
2. When the CPU responds to an interrupt, the IER register for different groups is not cleared. Therefore, for interrupt nesting involving different groups, there is no need to enable the IER register within the nested interrupt service routine. However, for interrupt nesting within the same group, the IER register must be enabled. Can I understand like this?
3. For 3 interrupt nesting, for example, EPWM1_ISR is nested by TIME0_ISR, and TIME0_ISR is nested by SCI_ISR. whether I need to enable IER bit of SCI_ISR. I think since TIME0_ISR is nested by SCI_ISR, when EPWM1_ISR is interrupted by TIME0_ISR，and TIME0_ISR  is executing, SCI_ISR is coming, it will interrupt TIME0_ISR. when SCI_ISR is finished, TIME0_ISR  goes on executing and then EPWM1_ISR. Is that right.
4. For  disabling Interrupts of  PIEIERx registers. we must  follow the procedure:

and
and DINT needs add at end of ISR.
why  above rule is violated, then spurious INTx.1 interrupts can be triggered. Could you elaborate on this or give me an example? I still have some questions about these and don't understand it in detail.  Thanks very much.
  • 0
    TI__Expert 6641 points

    Hi Yun,

    We have an interrupt SW prioritization example which demonstrates the software prioritization of interrupts through CPU Timer Interrupts. Software prioritization of interrupts is achieved by enabling interrupt nesting.

    Please have a look at these threads also -

     (+) TMS320F28379D: interrupt nesting - C2000 microcontrollers forum - C2000Tm︎ microcontrollers - TI E2E support forums

    (+) TMS320F280039C: Interrupt Nesting - C2000 microcontrollers forum - C2000Tm︎ microcontrollers - TI E2E support forums

    Let me go through the scenario that you have mentioned above and shall get back.
    Thanks
    Aswin
  • 0 in reply to Aswin P
    Intellectual 260 points

    Hi  Aswin,

    Any feedbacks? thanks!

  • 0 in reply to yun long
    TI__Genius 11280 points

    Hi Yun,

    I apologize for the delay. The interrupts you are trying to use are in the following locations in the ePIE table:

    EPWM1 - INT3.1

    TIMER0 - INT1.7

    SCIB_RX - INT9.3

    Given the order in the ePIE, the below would be the priorities in hardware:

    1. TIMER0 - INT1.7
    2. EPWM1 - INT3.1
    3. SCIB_RX - INT9.3

    If you are ok with the priority order above but just want to allow nesting of higher priority interrupts inside lower priority interrupts, you can simply add an EINT inside your low priority ISR's. For example:

    • Add EINT inside the SCIB_RX ISR to allow the EPWM1 amd TIMER0 interrupts to interrupt it
    • Add EINT inside the EPWM1 ISR to allow the TIMER0 interrupt to interrupt it

    If you want to change the order of these priorities to be different than are defined in the ePIE, that is when you would need to alter the IER register and use the masking defines.

    Since you are only wanting to nest interrupts that are all from different groups, no accesses to the PIEIER registers need to be made. You only need to work with the PIEIER registers if trying to change priorities within a group. For example, if you were using the TIMER0 interrupt and the XINT1 interrupt and wanted TIMER0 to have a higher priority. 

    Please let me know which priority order you are looking to use, and I can assist with specific code implementation if needed.

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    Intellectual 260 points

    Hi Delaney,

    Thank you for your patience and reply.

    1.Your answers solved my questions 1 and  3. colud you please explain the 4th question in detail? I don't quite understand it. And I would like SCIB_RX ISR to be the highest priority, then TIMER0_ISR and EPWM1 last. Because I found SCI communication can be disturbed by EPWM interrupt when the EPWM period is very small.

    2. For the sencond question, when the CPU responds to an interrupt, the IER register of different groups is not cleared by CPU.  Can I understand like this? Therefore, for interrupt nesting of different groups, there is no need to enable the IER register within the nested interrupt service routine. However, for interrupt nesting within the same group, the IER register must be enabled, so that the interrupt can be sent to CPU. Can I understand like this?

    Thanks very much!

  • +1 in reply to yun long
    TI__Genius 11280 points

    Hi Yun,

    I apologize for the delay.

    yun long said:
    colud you please explain the 4th question in detail? I don't quite understand it.

    Please see the 6 Read-Modify-Write Considerations When Using Bit Fields section (specifically 6.1 and 6.1.1) of the C28x Programming Guide linked here for an explanation about this.

    yun long said:
    And I would like SCIB_RX ISR to be the highest priority, then TIMER0_ISR and EPWM1 last.

    In that case, you would need to alter the IER register in all ISRs except the SCIB_RX ISR (top priority) using the masks.

    yun long said:
    For the sencond question, when the CPU responds to an interrupt, the IER register of different groups is not cleared by CPU.  Can I understand like this? Therefore, for interrupt nesting of different groups, there is no need to enable the IER register within the nested interrupt service routine. However, for interrupt nesting within the same group, the IER register must be enabled, so that the interrupt can be sent to CPU. Can I understand like this?

    This is correct, in normal operation when an ISR is branched to, the IER bits of other interrupt groups remain enabled. However, if you are trying to do nesting of 3 or more interrupts, you want a prioritization scheme. For example, in your case, you want to:

    from SCIB_RX ISR - no nesting

    from TIMER0 ISR - enable only SCIB_RX interrupt to nest

    from EPWM1 ISR - enable both/either SCIB_RX ISR or TIMER0 ISR to nest

    In this case, you want to disable the IER of the EPWM1 ISR inside the TIMER0 ISR to maintain the priority scheme. You are correct about needing to re-enable the IER for nesting within the same group since this is automatically cleared when the ISR is branched to.

    Please upvote any responses that were helpful to you Slight smile

    Best Regards,

    Delaney