TMS320F28069M: Interrupt nesting within same PIE interrupt group

Suresh leley

Part Number: TMS320F28069M
Other Parts Discussed in Thread: CONTROLSUITE

I am trying to port the PFC+Boost controller software from example code : C:\ti\controlSUITE\development_kits\HVMotorCtrl+PfcKit_v2.1\HVACI_Sensorless_PFC_F2803x

to HVMTR-EVM kit using control cardF28069MISO.

The documentation indicates that the _DPL_ISR in file PFC-DPL_ISR.asm is setup to interrupt the MotorInvISR().

From the code listing in HVACI_Sensorless_PFC.c the interrupts are setup as follows:

Interrupt PIE Group PIE Priority CPI INT CPU Priority Vector

ADC_INT1 1 1 1 5 DPL_ISR

ADC_INT2 1 2 1 5 MotorInvISR

Since both interrupts are coming form PIE group 1 and fed in to CPU INT1, it is not clear to me how the priority logic works. But based on Tms320F28069-FanmilyRef-spruh18h and C28X Interrupt Nesting app-note it seems, to allow DP_ISR to interrupt MotorInvISR you need to

1. clear PIEACK.INT1 to unblock interrupts from PIE group 1 and

2. set IER.INT1 to reenable cpu INT1 which is currently disabled as MotorInvISR is in progress.

I only see EINT at the start of MotorInvISR with comment // Motor ISR is interruptible by the digital power ISR which I believe only clears INTM.

Could you please provide some guidance on how priorities work in this particular case when two interrupts are from the same PIE group?

over 4 years ago

0 MatthewPate over 4 years ago

TI__Guru* 84230 points

Suresh,

The subject expert is out of the office today(8/23), but will be back tomm. You can expect a reply by end of business on 8/24.

Best,

Matthew

0 tlee over 4 years ago

TI__Guru 62975 points

Suresh,

The example that you are referencing does not appear to follow the recommended practices that are documented in the C28x Interrupt Nesting article. I would not be surprised to see undesired interrupt behavior if the interrupt scheme was extended beyond its current configuration. I would also not be surprised if the nesting is not actually working in its current form.

As you have pointed out, the example only uses two interrupts from a single group. If the nesting is working, it is only because the simplified scheme is aligned with the hardware-based PIE group arbitration logic.

When multiple interrupts from a single group are simultaneously active, the interrupt with the lowest enumerated value has priority:

In the case of the example, DPL_ISR (ADC_INT1 / INT1.1) is meant to interrupt the execution of MotorInvISR (ADC_INT2 / INT1.2). When EINT enables interrupts in MotorInvISR, the hardware PIE group arbitration logic naturally prioritizes the execution of DPL_ISR when ADC_INT1 is triggered.

One problem that I see however, is that the PIEACK bit for Group 1 does not seem to be cleared until the end of MotorInvISR, so ADC_INT1 is most likely being stalled until the end of MotorInvISR: