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TMS320F28379D: Nested interrupts within same PIE group

BrandonAzbell
Guru 63870 points
Part Number: TMS320F28379D
Other Parts Discussed in Thread: CONTROLSUITE

Customer has a scenario where they need to handle nested interrupts and has reviewed the following wiki article on this topic.

http://processors.wiki.ti.com/index.php/Interrupt_Nesting_on_C28x

They are using the TMS320F28379D and the caution in red indicates to consult the System, Control and Interrupts Guide if the application requires this to work through the procedure to avoid spurious interrupts.

Does this reference apply for the TMS320F28379D?

Is there documentation to point the customer to for handling this situation with the TMS320F28379D?

Thank you.

  • 0
    TI__Guru 63870 points

    And in looking at the latest Technical Reference Manual, in Section 2.4.4.4, it appears we are in a loop.

    2.4.4.4 Nesting Interrupts

    By default, interrupts do not nest. It is possible to nest and prioritize interrupts via software control of the

    IER and PIEIERx registers. Documentation and example code can be found in controlSUITE and on the TI

    Processors wiki:

    processors.wiki.ti.com/.../Interrupt_Nesting_on_C28x

  • 0 in reply to BrandonAzbell
    TI__Guru 53175 points
    The warning on the wiki page is primarily talking about the procedure in 2.4.4.3 on how to safely disable interrupts in PIEIER.

    However, in the example code for nesting interrupts, we make sure that we only modify PIEIER registers inside an ISR for its group and do so before the PIEACK bit is cleared. These are the limits set in the first two red paragraphs on the wiki page. If they aren't violated, you shouldn't need to follow the 2.4.4.3 procedure.

    Whitney