• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 84 subscribers
  • Views 365 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F280049-Q1: Will CPU error trigger an illegal ISR?

Wayne Huang
Genius 15705 points
Part Number: TMS320F280049-Q1

Dear Champs,

I am asking this for our customer.

If CPU has error itself during initialization or run time like fail to use ALU or any of the units inside C28x, will there be a triggered illegal ISR or any error that the user can be aware of?

Wayne Huang

  • 0
    TI__Guru** 113855 points

    Hi Wayne,

    There is no HW mechanism in CPU to detect that. It may eventually get into ITRAP but not guaranteed. There are some other check which can be performed to catch such issue before running application. I am looping in Krishna to provide more detail on that.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Genius 15705 points

    Dear Krishna,

    Would you please help confirm?

    Wayne

  • 0 in reply to Wayne Huang
    TI__Genius 15705 points

    Dear Krishna,

    Or should the user use C28x STL to detect this error?

    Wayne

  • 0 in reply to Wayne Huang
    TI__Expert 7985 points

    Hi Wayne, 

    There are two domains of operation that you are addressing here.  One is the startup, which takes care of initialization, POST operations etc., The other is run time, where the user application takes over the system control.  

    The C28x_STL is designed to run at POST only and provides a diagnostic coverage of 60%.  It tests various aspects of the CPU.  if an error is detected in any subsystem, the C28x_STL captures and reports it.  Please see details in the product release.

    In addition, there are several safety mechanisms that are supported by the device.  The details are provided in the safety manual.  The notification methods vary depending on the safety mechanism used.

    I hope this answers your question, please do not hesitate to ask more questions. 

    Regards,

    Krishna 

  • 0 in reply to Krishna Allam
    TI__Genius 15705 points

    Dear Krishna,

    For run-time, the user can leverage the safety mechanism to handle CPU errors.

    Like this case, to detect ALU error, the user can use CPU7 in the safety manual - 6.2.3 CPU Handling of Illegal Operation, Illegal Results and Instruction Trapping by using ITRAP and illegal ISR (vector 19) to handle this kind of error.

    Is our understanding correct?

    Wayne

  • +1 in reply to Wayne Huang
    TI__Expert 6325 points

    Wayne,

    CPU will only detect error when the instruction fetched is an illegal instruction. For faults in CPU, which will lead to error in calculation result, primary safety mechanism will be CPU1. For execution flow related faults,  internal / external watchdog timer will be helpful to detect faults.

    Han