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TMS320F28384S: The UART pins of CM core

Luke Chen
Expert 5090 points
Part Number: TMS320F28384S


Hi champs,

My customer imports CM UART example code for evaluation.

I check the register GPCCSEL3 and find that CPU1 doesn't assign GPIO84 and GPIO85 to CM core, but the UART function still works well under CCS debug mode.

Is it reasonable please?

Regards,

Luke

  • 0
    TI__Guru 60865 points

    Hi Luke,

    The GPCCSELx registers "Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin" so this would only be needed if the CM was going to directly control a GPIO in SW.  For peripherals, it is enough for the GPIO mux to be configured such that the peripheral's pins are brought out.  

  • 0 in reply to Devin Cottier
    TI__Expert 5090 points

    Devin,

    So when CM is using UART function, CPU1 is able to control the status of GPIO84 and GPIO85 if we don't assign GPIO84 and GPIO85 to CM?

    If we would like to make sure no other core changing the GPIO status, it is better to assign the GPIOs to CM core, is this correct?

    Regards,

    Luke

  • +1 in reply to Luke Chen
    TI__Guru 60865 points

    Hi Luke,

    If the GPIO mux is configured for CM-UART (or any mux selection other than "GPIOx"), writes to registers like GPIOSET or CLEAR won't do anything regardless of the owning core (the peripheral will control the pin instead of these registers).  Instead, I think what you want to prevent are further changes to the GPIO mux settings.  You can accomplish this by writing the lock bits in the GPIO control registers.  (So CPU1 configures the MUX for this pin, then locks the configurations for that pin).