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TMS320F28035: The phase-shifted full-bridge problem of PSFB peak current control based on TMS320FF28035

Green Deng
Expert 4490 points
Part Number: TMS320F28035
Other Parts Discussed in Thread: CONTROLSUITE, TIDM-02000

Dear team:

My customer has below questions, wish you can help answer:

I am debugging the phase shift full-bridge BUCK circuit based on F28035 chip, and realize phase shift by using peak current control. I use EPWM2 as the driver of arm, EPWM1 as the hysteresis arm, EPWM3 as the driver of side-side synchronous rectification, EPWM4 as the trigger ADC sampling, and COMP3A as the detection of peak current.Synchronize the EPWM2 clock at the same time to achieve phase shift.

However, the COMP3A comparator event cannot be triggered at the moment of low current, so the phase shift of EPWM2 cannot be realized.

EPWM2 module configuration is as follows:

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#define HSFB_PERIOD 205 //146kHz
void PWM_Config(void)
{
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the EPWM
EDIS;
//Time Base SubModule Register
EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // Set Immediate load
EPwm1Regs.TBPRD = HSFB_PERIOD;
EPwm1Regs.TBPHS.half.TBPHS = 0;
EPwm1Regs.TBCTR = 0;
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_CMPB; // Used to sync EPWM(n+1) "down-stream"
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// Counter compare submodule registers
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

COMP3A configuration is as follows:

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EALLOW;
AdcRegs.COMPHYSTCTL.bit.COMP3_HYST_DISABLE=0;
EDIS;
EALLOW;
GpioCtrlRegs.AIOMUX1.bit.AIO6 = 2;
EDIS;
EALLOW;
Comp3Regs.COMPCTL.bit.COMPDACEN = 1; // Power up Comparator locally
Comp3Regs.COMPCTL.bit.COMPSOURCE = 0; // Connect the inverting input to internal DAC
Comp3Regs.DACVAL.bit.DACVAL = 500; // Set DAC output - Input is Q15 - Convert to Q10
Comp3Regs.DACCTL.bit.DACSOURCE = 1; // 0 - DACVAL; 1 - Internal ramp for slope compensation
// Following lines of code are used when internal slope compensation is used
Comp3Regs.COMPCTL.bit.QUALSEL =5; // Comparator output must be active for 4 consecutive clocks before resetting the RAMP
Comp3Regs.DACCTL.bit.RAMPSOURCE = 3; // 0 - PMW1; 1 - PWM2, 2-PWM3, 3-PWM4
Comp3Regs.RAMPDECVAL_SHDW = 40;
EPwm4Regs.HRPCTL.bit.PWMSYNCSEL = 1; // PWM SYNC generated at CTR = ZRO for synchronizing internal ramp
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

The interrupt function is as follows:

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#define DACDRV_RAMP_In 38400 //环路计算值
if(TB_DIR_UP == EPwm1Regs.TBSTS.bit.CTRDIR) //PWM counter direction is UP
{
EPwm2Regs.TZCLR.all |= 0x0C;
EPwm2Regs.TZCTL.all = 0x0FFF;//0x0FFB; //Force EPWMxB to a low state
EPwm2Regs.AQCTLB.all = 0x0215; //CBU=HIGH, CAU=LOW, PRD=LOW, ZERO=LOW
EPwm2Regs.AQCTLA.all = 0x0124; //CBU=LOW, CAU=HIGH, PRD=LOW, ZERO=Nothing
EPwm2Regs.CMPA.half.CMPA = DB_AtoP;
EPwm2Regs.CMPB = (HSFB_PERIOD);
EPwm2Regs.DCFWINDOW = DB_PtoA+3;
EPwm1Regs.CMPA.half.CMPA = trig_up;
EPwm1Regs.CMPB = (HSFB_PERIOD+10); //set to 0, avoid CMPB to force EPWM2 sync event. Use DCAEVT1.sync to sync EPwm2 module.
EPwm1Regs.ETSEL.all=0x0B0D;
//Update RAMP value.
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Does the above configuration change the phase shift Angle by changing the value of DACDRV_RAMP_In?

Best regards

  • 0
    TI__Genius 15735 points

    Hi Green,

    Have you taken a look at the reference design code in the controlSUITE? It contains one peak current mode control phase shifted full bridge solution. 

    C:\ti\controlSUITE\development_kits\HVPSFB_v1.1

    Regards,

    Chen

  • 0 in reply to Chen Jiang ti
    Prodigy 165 points

    Yes,We have refer to this routine.And i want to know:

    (1) TI routines have F28027, but the interrupt inside is written in assembly, it looks more difficult, is there a pure C language routines?

    (2) At the same time, I found that if I reduce the value of DACDRV_RAMP_In, the phase shift Angle will indeed decrease, but if it is below 1700, the phase shift Angle will increase.(RAMPDECVAL_SHDW=15), how to set the slope and reference size.

  • 0 in reply to Feng Yang
    TI__Genius 15735 points

    Hi Feng,

    Feng Yang said:
    (1) TI routines have F28027, but the interrupt inside is written in assembly, it looks more difficult, is there a pure C language routines?

    We don't have C code ISR for F28027 device. We have another design TIDM-02000 which is based on our new F28004x device. That is also a Peak current mode controlled phase shifted full bridge which use C code ISR and some new device features.

    Feng Yang said:
    (2) At the same time, I found that if I reduce the value of DACDRV_RAMP_In, the phase shift Angle will indeed decrease, but if it is below 1700, the phase shift Angle will increase.(RAMPDECVAL_SHDW=15), how to set the slope and reference size.

    I am not sure why the phase angle start to increase. But you can refer to the section 3.3.4 of the TIDM-02000 user guide for slope compensation.

    Regards,

    Chen 

  • 0 in reply to Chen Jiang ti
    Prodigy 165 points

    Hi Chen,

    I want to ask a question is that how realize the open and close of the SR drive. As we know it used comparator event to open the SR driver,but how to close the drive.

  • 0 in reply to Feng Yang
    TI__Genius 15735 points

    Seems like you asked the question in another thread, so I will close this one.

    Regards,

    Chen