ePWM PWM1 Module Sync PWM2 Module

Mark,

You can use software sync before enabling the PWM's to make sure they start in sync, this can be done by writing to the TBCLKSYNC bit field in PCLKCR0 register, 

Ideally you would write this bit to zero, configure your PWM's have appropriate phase shifter counter value in the registers and then write a '1' to this bit field,

More information can be found at section 2.2.4, of the literature number  SPRUGE9E, section 3.1.1 of SPRUGL8A (system and interrupts guide),

Regards

Manish Bhardwaj

Thank you for your help Manish,

I will give that a try. - Mark

One quick follow-up question...

Can you point me in the right direction to configure the PWM system to have PWM module 3 completely independent of the modules PWM1 and PWM2?

- Mark

Mark typically you would like to start your system with known state,

the TBCLKSYNC i mentioned in the previous post, just ensures that all the TBCLK of the each PWM start at the same time, if you do not want them starting at the same time, you can disable the individual clock to the EPWM3,

SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 0;

and then enable it at some other instance, this would give an unknown phase between the modules, but this unknown is not truly random but a function of your code :)

Regards

Manish Bhardwaj

Thanks again for your help Manish

Hello Manish,

I am now using TBCLKSYNC bit in PCLKCR0, per your first response.  I am able to syncronize the start of PWM1 and PWM2 as desired.  Thank you.

My question is related to PWM3, which ideally would be completely independent from PWM1 and PWM2.  If PWM3 is running at a given duty cycle, when I write a zero to TBCLKSYNC, it disables the time based clock in all of the enable ePWM (including PWM3), which extends the period of PWM3 by the amount of time TBCLKSYNC is zero.  Is there any way to use TBCLKSYNC to synchronize the start of PWM1 and PWM2 without having an effect on an active PWM3?

Mark,

you are correct in your understanding of the module, once the TBCLKSYNC is issued it goes to all the PWM's. 

To solve your problem i would need to understand why you need PWM3 running before PWM1 and 2 phase are set correctly, 

A work around could be holding the PWM output as GPIO's , now do TBLCKSYNC, Now switch off PWM3 clock, and switch it back on to get a random phase w.r.t to PWM1 &2. Now configure PWM1 and 2 as PWM's.

Alternatively you can use the TBCTL.SWFSYNC force to enforce the counter values when you first start the PWM 1 and 2

Does this work for what you are trying to do?

I am using PWM3 as a completely independent PWM to a seperate device, so at the time when I want to turn on PWM1 and PWM2 (in sync at the same time), PWM3 could be active with any given PWM duty.  Please let me know if you have any other resulting suggestions.

I have tried several things related to SWFSYNC, but it appears that your suggestion on TBCLKSYNC is really what I need to do to ensure PWM1 and PWM2 start at the exact same time without any race conditions or software command execution differences.

Thanks for your help

-Mark

Mark,

I am unable to understand your apprehension about the software sync, I would agree you should not let the PWM be enabled before you force the software sync,

TBCLKSYNC does the same thing as SWFSYNC without stopping the clock to the PWM's,

if you still think this is an issue a diagram explaining where you see a problem would help,

Regards

Manish Bhardwaj

I will try:

• disabling PWM1 and PWM2
• then Writing a "1" to SWSYNC
• then reenabling PWM1 and PWM2

Another related question - I am starting to look at sync start of PWM1 and PWM2 with a phase delay.  What are the steps I need to do to successfully change frequency and phase delay and then sync start?

Issue #1:  This is what I am seeing:

• If I change freqency from 20Khz to 40Khz and modify the phase delay to 90 degrees, PWM2 does not start.
• If I change freqency from 20Khz to 40Khz but leave the phase delay at 0 degrees, PWM2 starts at 40KHz (I can subsequently change the phase)
• If I leave freqency at 20Khz and modify the phase delay to 90 degrees, PWM2 starts with the correct phase delay

Issue #2:  In cases where I am starting with a phase shift, since PWM2 leads PWM1 - I would always anticipate PWM2 to start before PWM1, however, sometimes PWM1 starts before PWM2.

Please let me know if you can provide some guidance on the correct way to modify PWM frequency with Phase delay and start PWM1 and PWM2 in a known way.

What is your PWM configuration? Can you share the code for that, 

While changing frequency for two PWM's you need to be carefull that you update the frequency of both the PWM's (i.e. change the TBPRD and load the appropriate CMPA and TBCTR value if need be) such that both the values take effect in the very next cycle. This can be guaranteed by updating the period and phase in an ISR.

For more please look at the way frequency modulation is done in the example project found here ,

controlSUITE\device_support\f2803x\v124\DSP2803x_examples_ccsv4\hrpwm_mult_ch_prdupdown_sfo_v6

The example uses high res , but the concept of updating the period and the CMPA are still valid,

Are you using High Resolution feature?

Hello Manish,

Just to close the loop on this... I tried

• disabling PWM1 and PWM2
• then Writing a "1" to SWFSYNC
• then reenabling PWM1 and PWM2

PWM1 and 2 were enabled with 0% DC.  In the background, I modifed PWM1 to 50% DC, then modifed PWM2 to 50%, then disabled PWM1 & 2 (with one write to PCLKCR1), wrote a "1" to SWFSYNC, then reenabled PWM 1&2 (with one write to PCLKCR1).  For the most part this was similar to TBCLKSYNC - but not all the time.  Sometimes PWM1 (which was modified first) would start a cycle before PWM2 started.

Hello Manish -

The PWM Config is as follows (please let me know if you have any recomendations):

Thank you, Mark

EALLOW;

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC  = 0;   // disable TBCLK within the ePWM

SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1;   // enable ePWM1

SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1;   // enable ePWM2

SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1;   // enable ePWM3

//PWM1

TBCTL.all = 0x0010

TBPRD = 3000

TBPHS.half.TBPHS = 0

TBCTR = 0

CMPCTL.bit.SHDWAMODE = 0

CMPCTL.bit.SHDWBMODE = 0

CMPCTL.bit.LOADAMODE = 0

CMPCTL.bit.LOADBMODE = 0

CMPA.half.CMPA = 0

CMPB = 0

AQCTLA.all = 0x0012

AQCTLB.all = 0x0012

DBCTL.all = 0x8003

DBRED = 0

DBFED = 0

ETSEL.bit.INTSEL = 1

ETSEL.bit.INTEN = 0

ETPS.bit.INTPRD = 3

//PWM2

TBCTL.all = 0x0004

TBPRD = 3000

TBPHS.half.TBPHS = 0

TBCTR = 0

CMPCTL.bit.SHDWAMODE = 0

CMPCTL.bit.SHDWBMODE = 0

CMPCTL.bit.LOADAMODE = 0

CMPCTL.bit.LOADBMODE = 0

CMPA.half.CMPA = 0

CMPB = 0

AQCTLA.all = 0x0012

AQCTLB.all = 0x0012

DBCTL.all = 0x8003

DBRED = 0

DBFED = 0

ETSEL.bit.INTSEL = 1

ETSEL.bit.INTEN = 0

ETPS.bit.INTPRD = 3

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;    // Enable TBCLK within the ePWM

EDIS;

Hi Mark,

I am having somewhat related problem.  I am toggling 3 PWM modules to control brushless motor.  When I dial in new settings for two PWM modules, changes go into effect one module at a time and separated by a full pwm period.

Have you figured out how to get rid of that delay?

I tried software synch (EPwm1Regs.TBCTL.bit.SWFSYNC), and making changes inside of clock disable/enable (SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC).  Neither one worked for me.

Thanks,

vlad

Hello Vlad,

Clock disable / enable worked for my application.  I have two channels that I need to start in sync.  The only draw back is my third channel is actively pwm-ing, suspending the clock has an impact on the period (which could extend either my duty cycle or my off time).   So I disabled TBCLK, started PWM1 and PWM2 and then enabled the clock to get them going in sync.

Do you have PWM1 configured as the master and PWM2 and PWM3 set as slave?

#define TBCTL_CONFIG_PWM1 (0x0010)
#define TBCTL_CONFIG_PWM2 (0x0004)

Make sure you do not have is phase shift enabled (as I do on my PWM channel 2).

One final thing that might be worth trying.  Try disabling shadow (mine is enabled above).  PRDLD (bit 3) = 1 to disable shadowing.  Depending on your mode of operation, this might be keeping changes to the register from taking effect unit the counter has reached zero.

I'm curious to know if any of the above helped.

Thanks Mark,

I appriciate your input, but non of the above suggestions worked.  I got a separate thread started.  Hopefully TI will spot my problem.

Just in case, here are my register settings...

// Init Timer-Base Control Register for EPWM1-EPWM3                 

   EPwm1Regs.TBCTL.bit.FREE_SOFT = SOFT_STOP_FLAG;

   EPwm1Regs.TBCTL.bit.PHSDIR    = PHSDIR_CNT_UP;

   EPwm1Regs.TBCTL.bit.CLKDIV    = CLKDIV_PRESCALE_X_1;

   EPwm1Regs.TBCTL.bit.HSPCLKDIV = HSPCLKDIV_PRESCALE_X_1;

   EPwm1Regs.TBCTL.bit.SYNCOSEL  = 1;  //send synch down stream         

   EPwm1Regs.TBCTL.bit.PRDLD     = 1;  //0-shadow mode, 1-immidiate mode

   EPwm1Regs.TBCTL.bit.PHSEN     = 0;  //no sync, make this pwm master

   EPwm1Regs.TBCTL.bit.CTRMODE   = TIMER_CNT_UP;

   EPwm2Regs.TBCTL.bit.FREE_SOFT = SOFT_STOP_FLAG;

   EPwm2Regs.TBCTL.bit.PHSDIR    = PHSDIR_CNT_UP;

   EPwm2Regs.TBCTL.bit.CLKDIV    = CLKDIV_PRESCALE_X_1;

   EPwm2Regs.TBCTL.bit.HSPCLKDIV = HSPCLKDIV_PRESCALE_X_1;

   EPwm2Regs.TBCTL.bit.SYNCOSEL  = 0;  //sync to master      

   EPwm2Regs.TBCTL.bit.PRDLD     = 1;  //0-shadow mode, 1-immidiate mode

   EPwm2Regs.TBCTL.bit.PHSEN     = 1;  //sync enable

   EPwm2Regs.TBCTL.bit.CTRMODE   = TIMER_CNT_UP;

This is master/slave setup from ePWM manual.  In this setup phase reg is enabled for PWM2.  From ePWM manual it makes sense for it to be enabled, but just in case I did also try to disable it.  Neither one helped. Shadow registeres were disabled.

If I find out more outside of e2e threads I will let you know.

Vlad