TMS320F28388D: TMS320F38388D: Optimization of shared memory between CPU1 and CLA.

Hi Jennifer,

The following two resources should help here:

https://software-dl.ti.com/C2000/docs/C2000_Multicore_Development_User_Guide/index.html

https://software-dl.ti.com/C2000/docs/optimization_guide/index.html

Thanks,

Ashwini

Thank you there are very useful but I can not find material about the use of volatile when using shared data memory between the CPU1 and CLA. It specifically indicates that volatile must be used between the main program and ISR or memory mapped peripherals but makes no statements about shared memory. 

I am using an LSxRAM to share data between CPU1 and CLA both have read and write access. Does the compiler automatically realize this is a shared area and variables in this RAM maybe changing out side of the main CPU program or the CLA task flows? Or is it required that volatile be added?

-Jennifer

Hi Jennifer,

The volatile keyword does help indicate to the compiler that something else in the system may change a variable and so assembly code will be generated accordingly by the compiler such that reads or writes to memory are not optimized away.

However one point to note is that if there are concurrent accesses from the C28 and CLA, then the arbitration logic would determine how the concurrent accesses get prioritized. Please see the device TRM "System Control and Interrupts" chapter section "Memory Controlller Module" - Access Arbitration for Shared RAM topic (3.12.1.7). If the CPU and CLA are performing concurrent read/write or write/write accesses, that could result in one overwriting the other or stale reads in which case you will need IPC as described in Multicore developement Guide to coordinate accesses to the shared data structure.

If the system is designed such that C28 and CLA will not be making concurrent accesses which involves a write then just the volatile usage should be sufficient.

Hope this helps.

Thanks,

Ashwini

I am not concerned about the arbitration. My question is for shared memory in the LSxRAMs that have R/W permission between the CLA and the CPU. Is the volatile word required to not optimize memory accesses away? Or does the compiler know from the R/W permissions in the project that these are volatile and do the right thing? I inherited a bunch of code and the key word volatile was not put on any of the structures but with optimizations turn on still works correctly. Did I get lucky or is there something under the hood that understands by default that these are volatile due to the permissions? 

I think what you are saying is I got lucky and I need to add volatile manually to any variable or structure shared between processors where writes by one processor and reads by another processor occurs to guarantee proper operation. This will just be a lot of work so want to make sure it is required.