TMS320F28069: ADC sample error is too large

Hi Emma,

Emma Wang said:

The abnormal AD Channel is ADCINA7, which is not mux with any other signals.

You mentioned that other ADC Channels had better performance, which other channels are those? Do the other channels have the same input circuit? 

Does a larger sample window size improve the results? 

Emma Wang said:

both for good device and bad device

This might be an indication that there is something wrong in the setup, maybe too much noise. Can the customer try switching to internal reference (just for debug) and seeing how that compares with using the external reference?

Best Regards,

Marlyn

Marlyn,

Thanks for your reply. But the thing is they use same input circuit and sample window for all the ADC channels.

For switching to internal reference, does that means they must destroy the external reference circuits?

and internal gain error seems larger than external gain error, so I am not sure whether the test is a must.

Emma

Hi Emma,

If all channels are under the same conditions then there is no need to switch to internal reference, especially if that causes a disruption. Do you know what other ADC channels are being used? Is it all of them? 

 Also, what is the pin package that the customer is using? Could you please send a picture of the top of one of the units?

As a test for A7, could you please ask the customer to perform the following,

1) Drive both A6 and A7 with known voltage-> Sample A6/A7-> Record the conversion results for both channels

2) Drive A6 to GND, Drive A7 with a known voltage-> Sample A7 -> Record A7 conversion result

3) Drive A6 to VREFHI voltage, Drive A7 with a known voltage -> Sample A7 -> Record A7 conversion result 

Best Regards,

Marlyn

Marlyn,

They are using TMS320F28067PZ.

And I will have them test agent ADC channels and give back the results.

BR

Emma

Marlyn,

Here is the test result based on your condition.

2451.F28069 ADC issue.xlsx

and they increase the sample window to 20 ADCCLK, it shows it shrinks the errors for small voltage but for some higher voltage on ADC pins, the error is similar as the original results.

And my question is, since there is a voltage on 0V input. could there is a leakage current which cause some small voltage on internal ADC capacitor, then caused the errors?

BR

Emma

Hi Emma,

Apologies for the delay in response due to US holidays. 

Thank you for sharing the results. It looks like A6 isnt affecting the conversion result on A7. 

Emma Wang said:

and they increase the sample window to 20 ADCCLK, it shows it shrinks the errors for small voltage but for some higher voltage on ADC pins, the error is similar as the original results.

Would it be possible to try a valid ACQPS value described in this application report: https://www.ti.com/lit/spracp5 

Data was collected for F2803x but it has the same ADC as the F2806x. 

Emma Wang said:

since there is a voltage on 0V input. could there is a leakage current which cause some small voltage on internal ADC capacitor, then caused the errors?

Could you please be more specific on what 0v input you are referring to?

Best Regards,

Marlyn

Marlyn,

Another question is , did we calibrate every ADC channel in fab?

BR

Emma

Hi Emma,

In the fab, calibration is performed to determine the right offsets for the ADC and these offsets are applied to all channels. So all channels should meet DS specs.

Best Regards,

Marlyn

Hi Marlyn,

I think I find the root cause.

They set sysclk to 90MHz and set the ADCCLK to 90MHz, too.

after set ADCCLK to 45MHz, the conversion is more correct.

However, I still have 2 questions.

1. Could you tell me if they set the ADCCLK to 90MHz, what will happen? since the max frequency of ADC module is 45MHz.

Customer want us to tell them.

2.How to understand gain error, can I think it is about 1% error(+/-40LSB/ 4096LSB)

It does not make sense a small input has 40LSB error.

BR

Emma