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Hi team,
Here's an issue from the customer may need your help:
The initial state of the serial port Tx side of the host is +6V, and when the serial port is started, the Tx side changes +6V to -6V, which causes the DSP28335 serial port to fail to communicate.
After testing, it's found that ScicRegs.SCICTL1.all = 0x0003; and ScicRegs.SCICTL1.all = 0x0023; this register needs to be reprogramed , then to communicate and receive data normally. The 28335 does not receive data after the host has transmitted data, the following is the serial initialization function:
void Sci_Init(void)
{
EALLOW;
GpioCtrlRegs.GPBPUD.bit.GPIO62 = 0; // Enable pull-up for GPIO62 (SCIRXDC)
GpioCtrlRegs.GPBPUD.bit.GPIO63 = 0; // Enable pull-up for GPIO63 (SCITXDC)
GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // Asynch input GPIO62 (SCIRXDC)
GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1; // Configure GPIO62 for SCIRXDC operation
GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1; // Configure GPIO63 for SCITXDC operation
EDIS;
ScicRegs.SCICCR.all = 0x0007;
ScicRegs.SCICTL1.all = 0x0003; // enable TX, RX, internal SCICLK,
ScicRegs.SCICTL2.all = 0x0003;
ScicRegs.SCICTL2.bit.TXINTENA = 0;
ScicRegs.SCICTL2.bit.RXBKINTENA =1;
ScicRegs.SCIHBAUD = 0x0000; // 115200 baudrate @LSPCLK = 37.5MHz.
ScicRegs.SCILBAUD = 0x0028;
ScicRegs.SCICTL1.all = 0x0023;
ScicRegs.SCIFFTX.all = 0x8000; // Disabled FIFO
EALLOW;
PieVectTable.SCIRXINTC = &ScicRx; //Place the SCIC interrupt sub-program address entry into the interrupt vector table
EDIS;
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable PIE vector table
PieCtrlRegs.PIEIER8.bit.INTx5 = 1; // Turn on Group 8 interrupt 5: SCICRX interrupt IER |= M_INT8;
}
If the Tx side of the host serial port has an initial state of -6V, the serial port of the 28335 does not become stuck when the host starts the serial port. The reason should be the initial state of the host serial port +6V, start the serial port, change to -6V, affecting the ScicRegs.SCICTL1 of the 28335 to control register. Online debug monitoring, the value of this register is not changed, but must be re-assigned to communicate properly. The customer would like to know what' the reason for that.
Could you help check this case? Thanks.
Best Regards,
Cherry
Hi Cherry,
I would encourage the SCI receive error interrupt to also be enabled (RXERRINTENA bit of the SCICTL1 register). The reason you might have to reprogram the SCICTL1 register is because of the SCI software reset (SWRESET) bit. This bit clears any errors that could have occurred during reception. Enabling the error interrupt will help us check if any errors occurred (from within the RX ISR) so we can start narrowing down the issue.
We also have this in-depth troubleshooting guide for the SCI: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1031947/faq-my-c2000-sci-is-not-transmitting-and-or-receiving-data-correctly-how-do-i-fix-this
Best Regards,
Marlyn