TMS320F280049: PLL configuration for external 8MHz clock

Hi,

I'm working on a F280049 project that initially used the LaunchXL-F280049C as the development kit. The actual kit used a 20MHz XTAL.

We already have a stable, low drift 8MHz clock on our board and we would like to use it as the clock source instead up the 20MHz crystal as used on the launchpad development board.

We have made the changes described below for the PLL configuration however the system clock is running at about 1/3 of the speed we expect.

The InitSysPll() function gets called in Main during startup and should set the PLL, for a system clock of 100MHz

It's not obvious what we are doing wrong?

In our firmware project that was derived from sample code TI provided for the Launchpad, the clock source, PLL setup etc. is defined in device.h as shown below:

//#############################################################################
// $TI Release: F28004x Support Library v1.05.00.00 $
// $Release Date: Thu Oct 18 15:43:57 CDT 2018 $
// $Copyright:
// Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/

#define DEVICE_OSCSRC_FREQ          20000000U

#define DEVICE_SETCLOCK_CFG         (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(10) |  \
                                     SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) |   \
                                     SYSCTL_PLL_ENABLE)

#define DEVICE_SYSCLK_FREQ          ((DEVICE_OSCSRC_FREQ * 10 * 1) / 2)  

-------------------------------------------------------------------------------------------------------------------------------------

And in f20004x_sysctrl.c the InitSysPll() function as InitSysPll(XTAL_OSC,IMULT_10,FMULT_0,PLLCLK_BY_2);

------------------------------------------------------------------------------------------------------------------------------------

Using the slower 8MHz source will require that we:

a) Change the PLL multiplier IMULT from 10 to 25

b) Set the XTALCR.SE bit for single ended mode instead of External Crystal mode

 I made the following changes for use with the 8MHz clock:

==================================================

#define DEVICE_OSCSRC_FREQ          8000000U    // changed from 20MHz to 8MHz

#define DEVICE_SETCLOCK_CFG         (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(25) |  \
                                     SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) |   \
                                     SYSCTL_PLL_ENABLE)

#define DEVICE_SYSCLK_FREQ          ((DEVICE_OSCSRC_FREQ * 25 * 1) / 2)     // changed from *10   to *25

======================================================

And in f20004x_sysctrl.c the InitSysPll() function as  InitSysPll(XTAL_OSC_SE,IMULT_25,FMULT_0,PLLCLK_BY_2);     // changed from IMULT_10  to IMULT_25

=====================================================================

The only thing that appears iffy is the "SYSCTL_OSCSRC_XTAL" used in the define for  DEVICE_SETCLOCK_CFG

My questions:

1) I can't seem to find the define for SYSCTL_OSCSRC_XTAL  anywhere, where would I find this define?

2) Should we be using a similar but different value for this parameter that reflects the single ended vs. XTAL configuration?

FYI as a sanity check I scoped the timing of the following and found GPIO12 to be high for 70ns, I was expecting 10 or 20ns. 

    GpioDataRegs.GPACLEAR.bit.GPIO12 = 1;   
    GpioDataRegs.GPASET.bit.GPIO12 = 1;   
    GpioDataRegs.GPACLEAR.bit.GPIO12 = 1;

In general timing seems to be running at 36% of what it should be, DELAY_US(100) yields a delay of 274us

In InitSysPll() there is a normal return when everything works as expected and some alternate code if the PLL has not stabilized, the function is returning via the normal return path.

I also setup a breakpoint in InitSysPll(), and inspected the .OSCOFF bit and it is cleared, the .SE bit is set and imult = 25, so everything appears to be as it should be for external clock.

This is the InitSysPLL function for clarity......

InitSysPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel)
{
    Uint32 timeout, retries, temp_syspllmult, pllLockStatus;
    bool status;
    // NOTE  clock_source = 5

    if(((clock_source & 0x3) == ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL)    &&
       (((clock_source & 0x4) >> 2) == ClkCfgRegs.XTALCR.bit.SE)           &&
                     (imult  == ClkCfgRegs.SYSPLLMULT.bit.IMULT)           &&
                     (fmult  == ClkCfgRegs.SYSPLLMULT.bit.FMULT)           &&
                     (divsel == ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV))
    {
         //
        // Everything is set as required, so just return
        //

        return;   // note returns from here

Below is the ClkCfgReg