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TMS320F240 PLL and External Clock synchronization

Dustin Holmes
Prodigy 40 points

I've got a question regarding the start-up logic in the c_int initialization routine, and setting up the ckcr0 and ckcr1 registers.  We've uncovered an issue at cold temperatures while setting up the PLL to synch to an externally sourced 20MHz clock.  The failure scenario is as such that there is a very large time constant at which memory (to include register settings) dissipates at cold.  We've been able to quantify that the colder the temperature the longer it takes for RAM to clear.  What we're seeing is in the range 11 seconds at 0 degrees C, and close to 0 seconds at ambient.  This is effecting our start up logic such that when we setup the PLL to lock onto the 20MHz external clock, we sometimes see at these cold temperatures where the registers are dissipating that we get a 40MHz clock instead.  This flows down to our SPI clock as well where we're getting 4 MHz instead of 2MHz.


Has TI ever seen this before, and is there any mechanism that we could use to know when this condition exists.  It seems like the registers are locked out for writing on a power-up reset at this particular time.  The effect of the wrong clock speed is that all of our timing is based off of number of clock cycles that would occur during a specific time period.  Running at twice the speed, we're executing too fast and setting system faults as a result. 

  • 0
    Prodigy 40 points

    To add another data point.  Yesterday it was observed during our investigation into this PLL clock setup, we had multiple occurrences where the CPU clock was running at half the requested clock speed (10MHz instead of 20MHz).  We have now seen doubling and halving of the clock.  This confirms that the registers are not taking the data that is being requested and latching with corrupt data.

  • 0 in reply to Dustin Holmes
    Prodigy 40 points

    Looks like this entire thing was tied to PO_RESET.  In our HW design, PO_RESET was tied high, and in looking through the documentation we are now going to apply it to Power valid in our design.  The main question still lingers, with the importance of PO_RESET, can we ensure that the start-up registers are in an known state and writable on a power-up reset over cold temperatures to ensure that the PLL comes up at the requested 20MHz.