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TMS320F280049: Jitter of HRPWM phase shift

Patrick Lenzen
Prodigy 240 points
Part Number: TMS320F280049

Hello everyone,

I'm just implementing a few optimizations of my code of the dual active bridge power converter.

To calculate the HRPWM TBPHS register values, I'm using the following example code:

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PHSFine = -(long)controlvalue; //controlvalue is negativ
PHS_reg_val = (long)(PHSFine * (EPwm3Regs.TBPRD*2 + 2))>>15;
tempPHS = (long)(PHSFine * (EPwm3Regs.TBPRD*2 + 2)) ;
tempPHS = tempPHS - ((long)PHS_reg_val << 15);
PHSHR_reg_val = tempPHS << 1; // convert to Q16
EPwm3Regs.TBPHS.all = (((long)PHS_reg_val) << 16) |
PHSHR_reg_val; // loses lower 8-bits
EPwm4Regs.TBPHS.all = (((long)PHS_reg_val) << 16) |
PHSHR_reg_val; // loses lower 8-bits
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

I have the following issue:

during the control phase, the PHSHR_reg_val is always near the maximum value and jumps between ~65000 and ~200. The PHS_reg_val value jumps also between two values.

This results in jitter on the PWM signal and is no smooth transition. 

If I add 16384 to PHSFine and subtract 100 from the register value PHS_reg_val , the jitter disappears. The code follows.

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PHSFine = 16384 +(long)controlvalue;
//Phase Shift Mode
PHS_reg_val = (long)(PHSFine * (EPwm3Regs.TBPRD*2 + 2))>>15;
tempPHS = (long)(PHSFine * (EPwm3Regs.TBPRD*2 + 2)) ;
tempPHS = tempPHS - ((long)PHS_reg_val << 15);
PHSHR_reg_val = tempPHS << 1; // convert to Q16
EPwm3Regs.TBPHS.all = (100-((long)PHS_reg_val) << 16) |
PHSHR_reg_val; // loses lower 8-bits
EPwm4Regs.TBPHS.all = (100-((long)PHS_reg_val) << 16) |
PHSHR_reg_val; // loses lower 8-bits
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

I cannot understand why there is a difference because normally the control loop should generate the same phase shift value.

Thanks for your help.

  • 0
    TI__Mastermind 23670 points

    Hi Patrick,

    Patrick Lenzen said:
    f I add 16384 to PHSFine and subtract 100 from the register value PHS_reg_val , the jitter disappears. The code follows.

    This is strange. Would it be possible to see how you have configured the EPWM module?

    Are you applying a synchronization pulse at every EPWM period or once on initialization?

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    Prodigy 240 points

    Thanks for your quick answer.

    The subroutines are called one after the other. Firstly, I call initEPWMstartup_project(void) and then initEPWM_project(void). 

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    void initEPWMstartup_project(void)
    {
    volatile struct EPWM_REGS *ePWM[] = {0, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs, &EPwm4Regs, &EPwm7Regs, &EPwm8Regs};
    volatile struct EPWM_REGS *ePWM_LV[] = {0, &EPwm1Regs, &EPwm2Regs, &EPwm7Regs, &EPwm8Regs};
    EALLOW;
    //stops the clock within the enabled EPWMs
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the EPWM
    SyncSocRegs.SYNCSELECT.bit.EPWM4SYNCIN = 0x0; //EPWM4 is also synchronized with the clock of EPWM1
    SyncSocRegs.SYNCSELECT.bit.EPWM7SYNCIN = 0x0; //EPWM4 is also synchronized with the clock of EPWM1
    int j = 0;
    for(j=1; j<=PWM_CH; j++)
    {
    (*ePWM[j]).TBCTL.bit.HSPCLKDIV = 0; // Change clock divider to /1
    (*ePWM[j]).TBPRD = SWPERIOD; // Period = (fSYSCLK/fs)/2 - 1 = 100e6/250e3 - 1 = 199
    (*ePWM[j]).TBPHS.bit.TBPHS = 0; // Set Phase register to 50% period
    (*ePWM[j]).TBCTR = 0; // clear TB counter
    (*ePWM[j]).TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Master: sync out pulse at counter zero - all other PWM TB_SYNC_IN (slave)
    (*ePWM[j]).TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Sawtooth carrier
    (*ePWM[j]).TBCTL.bit.PHSEN = TB_ENABLE; // Phase loading enable
    (*ePWM[j]).TBCTL.bit.PRDLD = TB_SHADOW; // use shadow register for TBPRD (synchronized pulses)
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0 in reply to Patrick Lenzen
    TI__Mastermind 23670 points

    Hi Patrick,

    Thank you for sharing your code. I will take a look through it and provide any feedback by tomorrow.

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    TI__Mastermind 23670 points

    Hi Patrick,

    If in up & down count mode, and doing both edge control then in this case you need to have action qualifier settings as follows: CMPxU = set, CMPxD = clear, no actions on TBCTR= PRD or ZRO. For AQCTLA registers, set on CAU and clear on CAD, for AQCLTB, set on CBU and clear on CBD

    The SYNCOSEL for EPWM1 is set as "TB_CTR_ZERO", which will send a sync pulse to the slave modules every time EPWM1's TBCTR counter is equal to 0. Note that when high-resolution period mode is enabled, an EPWMxSYNC pulse will introduce +/- 1 - 2 cycle jitter to the PWM (+/- 1 cycle in up-count mode and +/- 2 cycle in up-down count mode).

    You should set the  'Sync Out Pulse' to be configured to software, a software synchronization pulse should be issued only once during initialization and then only when the phase or period is changed. If a software sync pulse is applied while the PWM is running, the jitter will appear on the PWM output at the time of the sync pulse.

    Best Regards,

    Marlyn