TMS320F280049C: Pm_tformat_lib_f280049c cannot be used directly with LAUNCHXL-F280049C+BOOSTXL-POSMGR

Hi team,

Here's an issue from the customer may need your help:

Using the Pm_tformat_lib_f280049c library directly communicate and connect with the Domogawa encoder on the simulation board LAUNCHXL-F280049C+BOOSTXL-POSMGR, and failed. The Pm_tformat_lib source code is applied to the F28379D, with the main difference being the PWM4B interface. Below is the customer adapted Pm_tformat_lib_f2837x code, but failed with no CLB generated clock output.

1) Interface setting CLB4_BASE changed to CLB1_BASE:

void PM_tformat_setupPeriph(uint32_t devLSPCLKFreq)//
{
tformat_resetCLB();
tformat_initCLB1();

CLB_configLocalInputMux(CLB1_BASE, CLB_IN0, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB1_BASE, CLB_IN1, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB1_BASE, CLB_IN2, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB1_BASE, CLB_IN3, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB1_BASE, CLB_IN4, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB1_BASE, CLB_IN5, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB1_BASE, CLB_IN6, CLB_LOCAL_IN_MUX_GLOBAL_IN);
CLB_configLocalInputMux(CLB1_BASE, CLB_IN7, CLB_LOCAL_IN_MUX_GLOBAL_IN);

CLB_configGlobalInputMux(CLB1_BASE, CLB_IN0, CLB_GLOBAL_IN_MUX_EPWM4A);//wenr
CLB_configGlobalInputMux(CLB1_BASE, CLB_IN1, CLB_GLOBAL_IN_MUX_CLB_AUXSIG0);//
CLB_configGlobalInputMux(CLB1_BASE, CLB_IN2, CLB_GLOBAL_IN_MUX_EPWM4A);//
CLB_configGlobalInputMux(CLB1_BASE, CLB_IN3, CLB_GLOBAL_IN_MUX_EPWM4A);//
CLB_configGlobalInputMux(CLB1_BASE, CLB_IN4, CLB_GLOBAL_IN_MUX_EPWM4A);//
CLB_configGlobalInputMux(CLB1_BASE, CLB_IN5, CLB_GLOBAL_IN_MUX_EPWM4A);//
CLB_configGlobalInputMux(CLB1_BASE, CLB_IN6, CLB_GLOBAL_IN_MUX_EPWM4A);//
CLB_configGlobalInputMux(CLB1_BASE, CLB_IN7, CLB_GLOBAL_IN_MUX_EPWM4A);//

CLB_configGPInputMux(CLB1_BASE, CLB_IN0, CLB_GP_IN_MUX_GP_REG);
CLB_configGPInputMux(CLB1_BASE, CLB_IN1, CLB_GP_IN_MUX_EXTERNAL);
CLB_configGPInputMux(CLB1_BASE, CLB_IN2, CLB_GP_IN_MUX_EXTERNAL);
CLB_configGPInputMux(CLB1_BASE, CLB_IN3, CLB_GP_IN_MUX_EXTERNAL);
CLB_configGPInputMux(CLB1_BASE, CLB_IN4, CLB_GP_IN_MUX_EXTERNAL);
CLB_configGPInputMux(CLB1_BASE, CLB_IN5, CLB_GP_IN_MUX_EXTERNAL);
CLB_configGPInputMux(CLB1_BASE, CLB_IN6, CLB_GP_IN_MUX_EXTERNAL);
CLB_configGPInputMux(CLB1_BASE, CLB_IN7, CLB_GP_IN_MUX_GP_REG);//CLB_GP_IN_MUX_GP_REG

CLB_enableSynchronization(CLB1_BASE, CLB_IN0);
CLB_enableSynchronization(CLB1_BASE, CLB_IN1);

CLB_selectInputFilter(CLB1_BASE, CLB_IN0, CLB_FILTER_RISING_EDGE);
CLB_selectInputFilter(CLB1_BASE, CLB_IN1, CLB_FILTER_FALLING_EDGE);

tformat_initSPIFIFO(devLSPCLKFreq); // Initialize the SPI only
tformat_initCLBXBAR(); // Initialize the CLB XBARSPI only

}

2) The OUT2, OUT3, OUT4, OUT5 outputs of CLB4 are changed to OUT0, OUT1, OUT2, OUT3, OUT4, OUT5:

void PM_tformat_startOperation(void)//
{
EALLOW;
HWREG(CLB1_BASE + CLB_LOGICCTL + CLB_O_LOAD_EN) |= CLB_LOAD_EN_GLOBAL_EN
| CLB_LOAD_EN_STOP;

__asm(" RPT #10 || NOP");
// CLB_setOutputMask(CLB1_BASE, 0x3C, true);
CLB_setOutputMask(CLB1_BASE, 0x3f, true);//
__asm(" RPT #10 || NOP");
CLB_setGPREG(CLB1_BASE, 0x81);
}

3) GPIO:

void tformat_setupGPIO(void) {

//
// GPIO1 is SPI Clk slave
//
GPIO_setMasterCore(1, GPIO_CORE_CPU1);
GPIO_setPinConfig(GPIO_1_EPWM1_B);

//
// GPIO24 is the SPISIMOB
//
GPIO_setMasterCore(24, GPIO_CORE_CPU1);
GPIO_setPinConfig(GPIO_24_SPIB_SIMO);
GPIO_setQualificationMode(24, GPIO_QUAL_ASYNC);

//
// GPIO31 is the SPISOMIB
//
GPIO_setMasterCore(31, GPIO_CORE_CPU1);
GPIO_setPinConfig(GPIO_31_SPIB_SOMI);
GPIO_setQualificationMode(31, GPIO_QUAL_ASYNC);

//
// GPIO22 is the SPICLKB
//
GPIO_setMasterCore(22, GPIO_CORE_CPU1);
GPIO_setPinConfig(GPIO_22_SPIB_CLK);
GPIO_setQualificationMode(22, GPIO_QUAL_ASYNC);

//
// GPIO27 is the SPISTEB
//
GPIO_setMasterCore(27, GPIO_CORE_CPU1);
GPIO_setPinConfig(GPIO_27_SPIB_STE);
GPIO_setQualificationMode(27, GPIO_QUAL_ASYNC);

//
// GPIO7 is tformat TxEN
//
GPIO_setMasterCore(7, GPIO_CORE_CPU1);
GPIO_setPinConfig(GPIO_7_OUTPUTXBAR5);

//
// GPIO28 is PwrEN
//
GPIO_setMasterCore(28, GPIO_CORE_CPU1);
GPIO_setDirectionMode(28, GPIO_DIR_MODE_OUT);
}

4) XBAR:

void tformat_configXBAR(void)
{
//
// Connect InputXbar-INPUT1 to GPIO24 - SPISIMO
//

XBAR_setInputPin(XBAR_INPUT1, 24);//

XBAR_setCLBMuxConfig(XBAR_AUXSIG0, XBAR_CLB_MUX01_INPUTXBAR1);//InputXbar-INPUT1 TO XBAR_CLB_MUX01
XBAR_enableCLBMux(XBAR_AUXSIG0, XBAR_MUX01);
XBAR_setOutputMuxConfig(XBAR_OUTPUT5, XBAR_OUT_MUX01_CLB1_OUT4);//
XBAR_enableOutputMux(XBAR_OUTPUT5, XBAR_MUX01);

}

5) PWMB:

tformat_configEPWM1();

6) CLOCK:

#define TFORMAT_FREQ_DIVIDER    10 

Could you help check this case? Thanks.

Best Regards,

Cherry