TMS320F28374S: Flash API Error: Incorrect Data Buffer Length

Hi Denis,

In the linker command file of your application, can you check whether all the flash mapped sections are aligned on 128-bit boundary or not?  You can align them by using ALIGN(8) as shown in the linker command files provided in the C2000Ware.

Thanks and regards,

Vamsi

Hi, Vamsi.

I don't understand the structure and format of the linker command file well, so I can't say with certainty that all sections are aligned.

2837xS_Generic_FLASH_lnk.cmd:

MEMORY
{
PAGE 0 :  /* Program Memory */
          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
          /* BEGIN is used for the "boot to Flash" bootloader mode   */

   BEGIN           	: origin = 0x080000, length = 0x000002
   RAMM0           	: origin = 0x000123, length = 0x0002DD
   RAMD0           	: origin = 0x00B000, length = 0x000800
   RAMLS0          	: origin = 0x008000, length = 0x000800
   RAMLS1          	: origin = 0x008800, length = 0x000800
   RAMLS2      		: origin = 0x009000, length = 0x000800
   RAMLS3      		: origin = 0x009800, length = 0x000800
   RAMLS4      		: origin = 0x00A000, length = 0x000800
   RESET           	: origin = 0x3FFFC0, length = 0x000002

   /* Flash sectors */
   /* BANK 0 */
   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */

   /* BANK 1 */
   FLASHO           : origin = 0x0C0000, length = 0x002000	/* on-chip Flash */
   FLASHP           : origin = 0x0C2000, length = 0x002000	/* on-chip Flash */
   FLASHQ           : origin = 0x0C4000, length = 0x002000	/* on-chip Flash */
   FLASHR           : origin = 0x0C6000, length = 0x002000	/* on-chip Flash */
   FLASHS           : origin = 0x0C8000, length = 0x008000	/* on-chip Flash */
   FLASHT           : origin = 0x0D0000, length = 0x008000	/* on-chip Flash */
   FLASHU           : origin = 0x0D8000, length = 0x008000	/* on-chip Flash */
   FLASHV           : origin = 0x0E0000, length = 0x008000	/* on-chip Flash */
   FLASHW           : origin = 0x0E8000, length = 0x008000	/* on-chip Flash */
   FLASHX           : origin = 0x0F0000, length = 0x008000	/* on-chip Flash */
   FLASHY           : origin = 0x0F8000, length = 0x002000	/* on-chip Flash */
   FLASHZ           : origin = 0x0FA000, length = 0x002000	/* on-chip Flash */
   FLASHAA          : origin = 0x0FC000, length = 0x002000	/* on-chip Flash */
   FLASHBB          : origin = 0x0FE000, length = 0x001FF0	/* on-chip Flash */

//   FLASHBB_RSVD     : origin = 0x0FFFF0, length = 0x000010    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

PAGE 1 : /* Data Memory */
         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */

   BOOT_RSVD       : origin = 0x000002, length = 0x000121     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
   RAMD1           : origin = 0x00B800, length = 0x000800

   RAMLS5      : origin = 0x00A800, length = 0x000800

   RAMGS0      : origin = 0x00C000, length = 0x001000
   RAMGS1      : origin = 0x00D000, length = 0x001000
   RAMGS2      : origin = 0x00E000, length = 0x001000
   RAMGS3      : origin = 0x00F000, length = 0x001000
   RAMGS4      : origin = 0x010000, length = 0x001000
   RAMGS5      : origin = 0x011000, length = 0x001000
   RAMGS6      : origin = 0x012000, length = 0x001000
   RAMGS7      : origin = 0x013000, length = 0x001000
   RAMGS8      : origin = 0x014000, length = 0x001000
   RAMGS9      : origin = 0x015000, length = 0x001000
   RAMGS10     : origin = 0x016000, length = 0x001000
   RAMGS11     : origin = 0x017000, length = 0x000FF8
//   RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
}

SECTIONS
{
   /* Allocate program areas: */
   .cinit              : > FLASHB      PAGE = 0, ALIGN(8)
   .pinit              : > FLASHB,     PAGE = 0, ALIGN(8)
   .text               : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(8)
   codestart           : > BEGIN       PAGE = 0, ALIGN(8)

   /* Allocate uninitalized data sections: */
   .stack              : > RAMM1        PAGE = 1
#if defined(__TI_EABI__)
   .init_array         : > FLASHB,       PAGE = 0,       ALIGN(8)
   .bss                : > RAMLS5,       PAGE = 1
   .bss:output         : > RAMLS3,       PAGE = 0
   .bss:cio            : > RAMLS5,       PAGE = 1
   .data               : > RAMLS5,       PAGE = 1
   .sysmem             : > RAMLS5,       PAGE = 1
   /* Initalized sections go in Flash */
   .const              : > FLASHF,       PAGE = 0,       ALIGN(8)
#else
   .pinit              : > FLASHB,       PAGE = 0,       ALIGN(8)
   .ebss               : >> RAMLS5 | RAMGS0 | RAMGS1,    PAGE = 1
   .esysmem            : > RAMLS5,       PAGE = 1
   .cio                : > RAMLS5,       PAGE = 1
   /* Initalized sections go in Flash */
   .econst             : >> FLASHF      PAGE = 0, ALIGN(8)
#endif

   /* Initalized sections go in Flash */
   .switch             : > FLASHB      PAGE = 0, ALIGN(8)

   .reset              : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */

#ifdef __TI_COMPILER_VERSION__
    #if __TI_COMPILER_VERSION__ >= 15009000
        #if defined(__TI_EABI__)
            .TI.ramfunc : {} LOAD = FLASHD,
                                 RUN = RAMLS0,
                                 LOAD_START(RamfuncsLoadStart),
                                 LOAD_SIZE(RamfuncsLoadSize),
                                 LOAD_END(RamfuncsLoadEnd),
                                 RUN_START(RamfuncsRunStart),
                                 RUN_SIZE(RamfuncsRunSize),
                                 RUN_END(RamfuncsRunEnd),
                                 PAGE = 0, ALIGN(8)
        #else
            .TI.ramfunc : {} LOAD = FLASHD,
                             RUN = RAMLS0,
                             LOAD_START(_RamfuncsLoadStart),
                             LOAD_SIZE(_RamfuncsLoadSize),
                             LOAD_END(_RamfuncsLoadEnd),
                             RUN_START(_RamfuncsRunStart),
                             RUN_SIZE(_RamfuncsRunSize),
                             RUN_END(_RamfuncsRunEnd),
                             PAGE = 0, ALIGN(8)
        #endif
    #else
   ramfuncs            : LOAD = FLASHD,
                         RUN = RAMLS0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         RUN_SIZE(_RamfuncsRunSize),
                         RUN_END(_RamfuncsRunEnd),
                         PAGE = 0, ALIGN(8)
   #endif
#endif

   ramgs0           : > RAMGS0,    PAGE = 1
   ramgs1           : > RAMGS1,    PAGE = 1

   /* The following section definitions are for SDFM examples */
   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
   Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Hi

Could you provide a link to a document describing the structure and syntax of the linker command files?

Thanks.

Hi Denis,

I reviewed your linker cmd file.  I see that all the sections mapped to flash are aligned on 128-bit boundary.

Can you attach your map file?  I will check if there is any long section that is causing this issue.

Did you get any warning when compiling your application regarding any unmapped sections?

Regarding the linker command file, you can check this: https://software-dl.ti.com/ccs/esd/documents/c2000_c28x-compiler-understanding-linking.html 

Thanks and regards,

Vamsi

Hi, Vamsi.

CPU1_FLASH.zip

Compiling no errors or warnings.

Thanks

Hi Denis,

Thank you.  I will review and get back to you in couple of days.

Regards,

Vamsi

Hi Denis,

I did not see any long section causing this issue.

I will assign this to our flash kernel expert to help you further.

Thanks and regards,
Vamsi

Thanks, I'll wait.

Denis, 

Can you try changing the codestart section from BEGIN to an unused sector in BANK0, align it with the ALIGN(8) directive and see if there is any change?

Anu

Hi, Anu.

In the file 2837xS_Generic_FLASH_lnk.cmd replaced
   codestart : > BEGIN PAGE = 0, ALIGN(8)
on the
   codestart : > FLASHG PAGE = 0, ALIGN(8)
Result:

Thanks Denis. Can you send the map file of the project with this configuration?

Anu

hi, Anu

can_485_testBoot.zip

Denis, 

It looks like the codestart section is still mapped to BEGIN here - can you send the map file for when it is mapped to FLASHG?

Anu

I was looking at the wrong configuration, I see the codestart section mapped to FLASHG in the CPU1_FLASH folder. Did you make any modifications to the codestart section?

Anu

Yes.

"

Denis,

Can you try changing the codestart section from BEGIN to an unused sector in BANK0, align it with the ALIGN(8) directive and see if there is any change?
Anu

"

Denis, 

Did you change the actual content of the codestart section? I am wondering if there is an issue with fitting the contents of the codestart section into BEGIN. 

Anu

Anu,

can you be a little more detailed?

Denis, 

Did you make any changes in the code_start function in F2837xS_CodeStartBranch.asm file?

Anu

no

Can you try increasing the length of BEGIN by two and decreasing the length of FLASHA by 2 and remapping codestart there?

If this is an acceptable change for you, you can proceed like this. I am not sure why BEGIN with a length of 0x2 is not being written to, this is something we will need to look into further internally. 

Anu

Hi, Anu.

1.

   BEGIN               : origin = 0x080000, length = 0x000004

2.

   FLASHA           : origin = 0x080004, length = 0x000FFF    /* on-chip Flash */

3.

   codestart           : > BEGIN       PAGE = 0, ALIGN(8)

Not sure what's right.

The result is the same.

The length of FLASHA should be 0xFFC. Was a compilation error not thrown when the length of FLASHA was 0xFFF?

Thanks, Anu.

There were no errors, the compilation was smooth.
0xFFC as well. No changes..

Denis, 

By no changes, do you mean you are able to run the flash kernel correctly and download the image? If so, will this solution of changing the lengths of BEGIN and FLASHA work for you?A

Anu

Hi, Anu.

Yes, Flash kernel and image are flashed.

Denis, 

That's good, do you have any further questions?

Anu