TMS320F28069: CAN status bit

Hi Hareesh,

Thanks for your support.

Hareesh Janakiraman said:

When CCR bit is set by the CAN module under a bus-off condition

Bus-off condition, is this referring to unplugging the CAN line? 

And now the case is when hardware is disturbed, the CAN connection fails completely and the CAN connection does not return to normal even when external interference is removed. 

Thanks and regards,

Cherry

Then current situation is how can I make CAN link recover even this error happen ? Or the recovery is possible only after power on-off ? 
Or what can I do under current situation , like re-init some register?

Hi Hareesh,

Xiaohuang Li is my customer and you could directly discuss this issue in this thread, if you need any further assistance please let me know.

Thanks and regards,

Cherry

I am still confused why CCE bit can be set after DSP has init eCAN successfully.

My issue is CCE bit is set after several times plug-unplug CAN device.

Can I use the way you have mentioned as above to resolve my issue ? 

Now, seems the issue can resolved after power-off and power on again. This is not my intention. My intention is to recover CAN tx-rx without power-off & power-on;

I found another phenomenon that after CAN RX-TX does not work, then I watch CANES register, no TM can be set to 1 even if the DSP software has  a large quantities of data is being sent.


Per my understanding, event TX will result in TM set ,right ? but now, it is not;
Why this happen ?

Thanks for your reply,

I find once the issue as mentioned as above happen, If I re-invoke InitECana(void) will help bring eCAN RX-Tx back to normal status.

BTW, if SRES bit is set again, must eCAN be re-init or nor ?

do you mean this setting will help ?

{
/* Create a shadow register structure for the CAN control registers. This is
needed, since only 32-bit access is allowed to these registers. 16-bit access
to these registers could potentially corrupt the register contents or return
false data. */

struct ECAN_REGS ECanaShadow;

//////////////////////////////////////////////////////
// 0~23 is TX
//////////////////////////////////////////////////////
CONFIG_TX_MSG_BOXS();

//////////////////////////////////////////////////////
// 24~31 is Rx
//////////////////////////////////////////////////////
CONFIG_RCV_MSG_BOXS();

// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
// as a matter of precaution.

ECanaRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */
ECanaRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */

ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
ECanaRegs.CANGIF1.all = 0xFFFFFFFF;

/* Configure bit timing parameters for eCANA*/

EALLOW;
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

// Wait until the CPU has been granted permission to change the configuration registers
do
{
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set..

// Step 6. Program the master control register (CANMC) as follows:
// 1. Clear CCR (CANMC.12) = 0
// 2. Clear PDR (CANMC.11) = 0
// 3. Clear DBO (CANMC.10) = 0
// 4. Clear WUBA (CANMC.9)= 0
// 5. Clear CDR (CANMC.8) = 0
// 6. Clear ABO (CANMC.7) = 1
// 7. Clear STM (CANMC.6) = 0
// 8. Clear SRES (CANMC.5) = 0
// 9. Clear MBNR (CANMC.4-0) = 0

ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
ECanaShadow.CANMC.bit.PDR = 0 ; // Set PDR = 0
ECanaShadow.CANMC.bit.DBO = 0 ; // Set DBO = 0
ECanaShadow.CANMC.bit.WUBA = 0 ; // Set WUBA = 0
ECanaShadow.CANMC.bit.CDR = 0 ; // Set CDR = 0
ECanaShadow.CANMC.bit.ABO = 1 ; // Set ABO = 1
ECanaShadow.CANMC.bit.STM = 0 ; // Set STM = 0
ECanaShadow.CANMC.bit.SRES = 0 ; // Set SRES = 0
ECanaShadow.CANMC.bit.MBNR = 0 ; // Set MBNR = 0
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

// Wait until the CPU no longer has permission to change the configuration registers
do
{
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared..
EDIS;

EALLOW;
ECanaRegs.CANMIM.all = 0xFFFFFFFF;
ECanaRegs.CANMIL.all = 0;
ECanaRegs.CANGIF0.all = 0xFFFFFFFF;
ECanaRegs.CANGIM.all = 0x0003FF07;
EDIS;
}