TMS320F28377D: PWM INITIALIZATION

VISHAL SAPAARA

Part Number: TMS320F28377D

Dear all,

I have configured three level inverter PWM in my system and I am getting some error initially and when there is no COMPARE event at that time 1B AND 2B are HIGH unintentionally because they are complementally .

I have attached the image for PWM given to one leg for your ref.

ch-1 , ch-2 , ch-3 ,ch-4. are the scope Channel number and scope image with T3 AND T4 ARE HIGH when T1 AND T2 are low. this occurs only during initialization and then its all ok.

i have attached code and of initialization and EnablePWM function .this enablepwm is only call once during start-up at every staring event only.

please suggest me how can i make T3 And T4 both Low .

void InitPwm1(void)
{
    EALLOW;
    EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD;
    EPwm1Regs.TBCTR = 0x0000;
    EPwm1Regs.TBCTL.bit.PHSDIR = TB_UP;// Clear counter

    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
    #ifdef SLAVE_MODE

    EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE;

    #else

    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;

    #endif

    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

    EPwm1Regs.CMPC = 0;

	#ifdef SLAVE_MODE

	EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

	#else
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;

	#endif
    //SyncSocRegs.SYNCSELECT.bit.SYNCOUT = 0;
    SyncSocRegs.SYNCSELECT.bit.EPWM7SYNCIN = 0; //
	SyncSocRegs.SYNCSELECT.bit.EPWM4SYNCIN = 0;


    EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm1Regs.DBCTL.bit.POLSEL  = DB_ACTV_HIC;
 //   EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;

    EPwm1Regs.DBFED.bit.DBFED= FED_TIME*PWM_BASE_FREQUENCY;
    EPwm1Regs.DBRED.bit.DBRED= FED_TIME*PWM_BASE_FREQUENCY;

    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
//    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
///    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;


//    SyncSocRegs.SYNCSELECT.bit.EPWM4SYNCIN = 0;

#ifdef EPWM7_SOCA
    EPwm1Regs.ETSEL.bit.SOCAEN=1;
    EPwm1Regs.ETSEL.bit.SOCASEL= SOC_EVENT_TIME;
    EPwm1Regs.ETPS.bit.SOCAPRD = ET_1ST;
#endif

#ifdef EPWM1INTENABLE
    EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_PRDZERO;     // Select INT on Zero event
    EPwm1Regs.ETSEL.bit.INTEN = 1;                // Enable INT
    EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;           // Generate INT on 3rd event*/
#endif

    EPwm1Regs.TBPHS.bit.TBPHS = 0;
    //EPwm1Regs.CMPA.bit.CMPA    =   EPWM1_TIMER_TBPRD>>1;
     //EPwm1Regs.CMPB.bit.CMPB    =   EPWM1_TIMER_TBPRD>>1;
     EDIS;
}

void InitPwm2(void)
{
    EALLOW;
    EPwm2Regs.TBPRD = EPWM1_TIMER_TBPRD_TOP;       // Set timer period 801 TBCLKs
    EPwm2Regs.TBPHS.bit.TBPHS  = EPWM1_TIMER_TBPRD;

    EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP;

    EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
    EPwm2Regs.TBCTL.bit.PHSEN   = TB_ENABLE;              // Disable phase loading
    EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;

    EPwm2Regs.TBCTL.bit.SYNCOSEL=TB_SYNC_IN;

    EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm2Regs.DBCTL.bit.POLSEL  = DB_ACTV_HIC;
 //   EPwm2Regs.DBCTL.bit.OUT_MODE= DB_FULL_ENABLE;

    EPwm2Regs.DBFED.bit.DBFED= FED_TIME*PWM_BASE_FREQUENCY;
    EPwm2Regs.DBRED.bit.DBRED= FED_TIME*PWM_BASE_FREQUENCY;

    EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
 //   EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; // Load on Zero
//    EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;

#ifdef EPWM8_SOCA
    EPwm2Regs.ETSEL.bit.SOCAEN=1;
    EPwm2Regs.ETSEL.bit.SOCASEL=SOC_EVENT_TIME;
    EPwm2Regs.ETPS.bit.SOCAPRD = ET_1ST;
#endif
    EDIS;
}

void InitPwm3(void)
{
    EALLOW;
    EPwm3Regs.TBPRD = EPWM1_TIMER_TBPRD_TOP;       // Set timer period 801 TBCLKs

    EPwm3Regs.TBCTL.bit.PHSDIR= TB_UP;
    EPwm3Regs.TBCTR = 0x0000;                  // Clear counter

    EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
    EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Disable phase loading
    EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;

    EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

    EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
  //  EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;

    EPwm3Regs.DBFED.bit.DBFED= FED_TIME*PWM_BASE_FREQUENCY;
    EPwm3Regs.DBRED.bit.DBRED= FED_TIME*PWM_BASE_FREQUENCY;

    EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
 //   EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;
//    EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;

#ifdef EPWM9_SOCA
    EPwm3Regs.ETSEL.bit.SOCAEN=1;
    EPwm3Regs.ETSEL.bit.SOCASEL=SOC_EVENT_TIME;
    EPwm3Regs.ETPS.bit.SOCAPRD = ET_1ST;
#endif
//        EPwm3Regs.ETSEL.bit.SOCAEN=1;
//        EPwm3Regs.ETSEL.bit.SOCASEL=ET_CTR_ZERO;
//        EPwm3Regs.ETPS.bit.SOCAPRD = ET_1ST;

/*    EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     // Select INT on Zero event
    EPwm3Regs.ETSEL.bit.INTEN = 1;                // Enable INT
    EPwm3Regs.ETPS.bit.INTPRD = ET_3RD;           // Generate INT on 3rd event*/

    EPwm3Regs.TBPHS.bit.TBPHS = EPWM1_TIMER_TBPRD;
     EDIS;
}

void InitPwm7(void)
{
    EALLOW;
//        EPwm7Regs.TBPRD = EPWM1_TIMER_TBPRD_TOP;       // Set timer period 801 TBCLKs

    EPwm7Regs.TBPRD = EPWM1_TIMER_TBPRD;

    EPwm7Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
    EPwm7Regs.TBCTL.bit.PHSDIR= TB_UP;
    EPwm7Regs.TBCTR = 0x0000;                  // Clear counter

    EPwm7Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
    EPwm7Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Disable phase loading
    EPwm7Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm7Regs.TBCTL.bit.CLKDIV = TB_DIV1;

    EPwm7Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm7Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
  //  EPwm7Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;

    EPwm7Regs.DBFED.bit.DBFED= FED_TIME*PWM_BASE_FREQUENCY;
    EPwm7Regs.DBRED.bit.DBRED= FED_TIME*PWM_BASE_FREQUENCY;

    EPwm7Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
 //   EPwm7Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm7Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
 //   EPwm7Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

#ifdef EPWM9_SOCA
    EPwm7Regs.ETSEL.bit.SOCAEN=1;
    EPwm7Regs.ETSEL.bit.SOCASEL=SOC_EVENT_TIME;
    EPwm7Regs.ETPS.bit.SOCAPRD = ET_1ST;
#endif
//        EPwm7Regs.ETSEL.bit.SOCAEN=1;
//        EPwm7Regs.ETSEL.bit.SOCASEL=ET_CTR_ZERO;
//        EPwm7Regs.ETPS.bit.SOCAPRD = ET_1ST;

/*    EPwm7Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     // Select INT on Zero event
    EPwm7Regs.ETSEL.bit.INTEN = 1;                // Enable INT
    EPwm7Regs.ETPS.bit.INTPRD = ET_3RD;           // Generate INT on 3rd event*/

    EPwm7Regs.TBPHS.bit.TBPHS =0;

   //  EPwm7Regs.CMPA.bit.CMPA    =   EPwm3_TIMER_TBPRD>>1;
     //EPwm7Regs.CMPB.bit.CMPB    =   EPwm3_TIMER_TBPRD>>1;
     EDIS;
}

void InitPwm8(void)
{
    EALLOW;
    EPwm8Regs.TBPRD = EPWM1_TIMER_TBPRD_TOP;       // Set timer period 801 TBCLKs
    EPwm8Regs.TBCTL.bit.PHSDIR= TB_UP;
    EPwm8Regs.TBCTR = 0x0000;                  // Clear counter
   // EPwm8Regs.CMPA.bit.CMPA = 0;
    EPwm8Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
    EPwm8Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Disable phase loading
    EPwm8Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm8Regs.TBCTL.bit.CLKDIV = TB_DIV1;

    EPwm8Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

    EPwm8Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm8Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
  //  EPwm8Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;

    EPwm8Regs.DBFED.bit.DBFED= FED_TIME*PWM_BASE_FREQUENCY;
    EPwm8Regs.DBRED.bit.DBRED= FED_TIME*PWM_BASE_FREQUENCY;

    EPwm8Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
 //   EPwm8Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm8Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; // Load on Zero
 //   EPwm8Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;

#ifdef EPWM9_SOCA
    EPwm8Regs.ETSEL.bit.SOCAEN=1;
    EPwm8Regs.ETSEL.bit.SOCASEL=SOC_EVENT_TIME;
    EPwm8Regs.ETPS.bit.SOCAPRD = ET_1ST;
#endif
//        EPwm8Regs.ETSEL.bit.SOCAEN=1;
//        EPwm8Regs.ETSEL.bit.SOCASEL=ET_CTR_ZERO;
//        EPwm8Regs.ETPS.bit.SOCAPRD = ET_1ST;

/*    EPwm8Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     // Select INT on Zero event
    EPwm8Regs.ETSEL.bit.INTEN = 1;                // Enable INT
    EPwm8Regs.ETPS.bit.INTPRD = ET_3RD;           // Generate INT on 3rd event*/

    EPwm8Regs.TBPHS.bit.TBPHS = EPWM1_TIMER_TBPRD;

   //  EPwm8Regs.CMPA.bit.CMPA    =   EPwm3_TIMER_TBPRD>>1;
     //EPwm8Regs.CMPB.bit.CMPB    =   EPwm3_TIMER_TBPRD>>1;
     EDIS;
}

void InitPwm9(void)
{
    EALLOW;
//        EPwm9Regs.TBPRD = EPWM1_TIMER_TBPRD_TOP;       // Set timer period 801 TBCLKs
    EPwm9Regs.TBPRD = EPWM1_TIMER_TBPRD;

          // Phase is 0
    EPwm9Regs.TBCTL.bit.PHSDIR= TB_UP;
    EPwm9Regs.TBCTR = 0x0000;                  // Clear counter

    EPwm9Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
    EPwm9Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Disable phase loading
    EPwm9Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm9Regs.TBCTL.bit.CLKDIV = TB_DIV1;

    EPwm9Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

    EPwm9Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm9Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
  //  EPwm9Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;

    EPwm9Regs.DBFED.bit.DBFED= FED_TIME*PWM_BASE_FREQUENCY;
    EPwm9Regs.DBRED.bit.DBRED= FED_TIME*PWM_BASE_FREQUENCY;

    EPwm9Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
 //   EPwm9Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm9Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
  //  EPwm9Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

#ifdef EPWM9_SOCA
    EPwm9Regs.ETSEL.bit.SOCAEN=1;
    EPwm9Regs.ETSEL.bit.SOCASEL=SOC_EVENT_TIME;
    EPwm9Regs.ETPS.bit.SOCAPRD = ET_1ST;
#endif
//        EPwm9Regs.ETSEL.bit.SOCAEN=1;
//        EPwm9Regs.ETSEL.bit.SOCASEL=ET_CTR_ZERO;
//        EPwm9Regs.ETPS.bit.SOCAPRD = ET_1ST;

/*    EPwm9Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     // Select INT on Zero event
    EPwm9Regs.ETSEL.bit.INTEN = 1;                // Enable INT
    EPwm9Regs.ETPS.bit.INTPRD = ET_3RD;           // Generate INT on 3rd event*/

    EPwm9Regs.TBPHS.bit.TBPHS =0;

   //  EPwm9Regs.CMPA.bit.CMPA    =   EPwm3_TIMER_TBPRD>>1;
     //EPwm9Regs.CMPB.bit.CMPB    =   EPwm3_TIMER_TBPRD>>1;
     EDIS;
}

void EnablePwm(void)
{
	fmR=0.0;
	fmY=0.0;
	fmB=0.0;

    Idout = 0.1;
    flag.bit.InvStatus=1;
    //flag.bit.OpenLoopInverter=1;
	InvParaInitialisation();
    g_uiSoftStartDone=0;
    inverterStartupCall();
    if(flag.bit.MPS_Operating_Mode==UF_MODE)
    {
    	//flag.bit.UF_ssDone=0;
		g_structVr.term.Ref = config.IntrnlParams.VRampRate/config.CalibData.VaRms;
		g_structVy.term.Ref = config.IntrnlParams.VRampRate/config.CalibData.VbRms;
		g_structVb.term.Ref = config.IntrnlParams.VRampRate/config.CalibData.VcRms;
		//starting uf mode voltage from 50Hz. change to intial value if needed to start from any other value
		//finalW = (config.UserParams.Fout*twoPI);
		//flag.bit.UF_ssDone=0;
		flag.bit.Fre_ssDone =0;
    }

    EALLOW;

    EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm7Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm8Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm9Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;

//
//	EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;
//	EPwm1Regs.AQCTLA.bit.PRD = AQ_CLEAR;
//	//EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR;
//	//EPwm1Regs.AQCTLB.bit.CAD = AQ_SET;
//
//	EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR;
//	EPwm2Regs.AQCTLA.bit.PRD = AQ_SET;
//
//	EPwm3Regs.AQCTLA.bit.ZRO = AQ_CLEAR;
//	EPwm3Regs.AQCTLA.bit.PRD = AQ_SET;
//
//    EPwm7Regs.AQCTLA.bit.ZRO = AQ_SET;
//    EPwm7Regs.AQCTLA.bit.PRD = AQ_CLEAR;
//
//    EPwm8Regs.AQCTLA.bit.ZRO = AQ_CLEAR;            // Set PWM1A on event A, up
//    EPwm8Regs.AQCTLA.bit.PRD = AQ_SET;          // Clear PWM1A on event A,
//
//    EPwm9Regs.AQCTLA.bit.ZRO = AQ_SET;          // Clear Pwm3A on event A,
//    EPwm9Regs.AQCTLA.bit.PRD = AQ_CLEAR;           // Set Pwm3A on event A, up

/*
	EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
	EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;
	//EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR;
	//EPwm1Regs.AQCTLB.bit.CAD = AQ_SET;

	EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;
	EPwm2Regs.AQCTLA.bit.CAD = AQ_SET;

	EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR;
	EPwm3Regs.AQCTLA.bit.CAD = AQ_SET;

    EPwm7Regs.AQCTLA.bit.CAU = AQ_CLEAR;
    EPwm7Regs.AQCTLA.bit.CAD = AQ_SET;

    EPwm8Regs.AQCTLA.bit.CAU = AQ_CLEAR;            // Set PWM1A on event A, up
    EPwm8Regs.AQCTLA.bit.CAD = AQ_SET;          // Clear PWM1A on event A,

    EPwm9Regs.AQCTLA.bit.CAU = AQ_CLEAR;          // Clear Pwm3A on event A,
    EPwm9Regs.AQCTLA.bit.CAD = AQ_SET;           // Set Pwm3A on event A, up
    */

	EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
	EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;
	//EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR;
	//EPwm1Regs.AQCTLB.bit.CAD = AQ_SET;

	EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;
	EPwm2Regs.AQCTLA.bit.CAD = AQ_SET;

	EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR;
	EPwm3Regs.AQCTLA.bit.CAD = AQ_SET;

    EPwm7Regs.AQCTLA.bit.CAU = AQ_CLEAR;
    EPwm7Regs.AQCTLA.bit.CAD = AQ_SET;

    EPwm8Regs.AQCTLA.bit.CAU = AQ_CLEAR;            // Set PWM1A on event A, up
    EPwm8Regs.AQCTLA.bit.CAD = AQ_SET;          // Clear PWM1A on event A,

    EPwm9Regs.AQCTLA.bit.CAU = AQ_CLEAR;          // Clear Pwm3A on event A,
    EPwm9Regs.AQCTLA.bit.CAD = AQ_SET;           // Set Pwm3A on event A, up



//    GpioDataRegs.GPADAT.bit.GPIO15=0;
//    GpioDataRegs.GPADAT.bit.GPIO17=0;

    TzEnable();
EDIS;

}

over 3 years ago

0 Marlyn Rosales Castaneda20 over 3 years ago

TI__Mastermind 25800 points

Hi Vishal,

Because you are using the dead-band submodule to create complementary pairs you have two options to make all output low upon initialization.

1) Keep the pins as GPIOs instead of EPWM pins until initialization is over (after TBCLKSYNC=1)

2) Apply a software force (TZFRC register) within the trip zone submodule to make the outputs low. (clear the software force after TBCLKSYNC=1)

Best Regards,

Marlyn

0 VISHAL SAPAARA over 3 years ago in reply to Marlyn Rosales Castaneda20

Prodigy 60 points

Hi Marlyn Rosales ,

This PIN become high when i call EnablePwm() function after completion of PWM initialization.

when it is into EnablePwm() at that time when i call below instruction at that create the T3 and T4 to high.

EPWM1 & EPWM2 is for R-phase and EPWM3 & EPWM7 IS FOR Y PHASE and so on.

EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm7Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm8Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm9Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;

please suggest how can i make this T3 and T4 low.

PWM initialization happens in main() during starting of program ,

1. first this function is call

void testing_gpio_config(void)
{
unsigned int i;
EALLOW;

//44-45, 59-66 DI
//12 to 17 DO
//31 to 41, 48 to 58 DO
//3 t 7, 80 to 83, 86 to 92 DO
/*-------------------------------------------*/
for(i=0;i<=5;i++) //pwm
{
GPIO_SetupPinMux(i,0,1);
GPIO_SetupPinOptions(i, GPIO_OUTPUT, GPIO_PUSHPULL);
}

for(i=12;i<=15;i++) //pwm
{
GPIO_SetupPinMux(i,0,1);
GPIO_SetupPinOptions(i, GPIO_OUTPUT, GPIO_PUSHPULL);
}
for(i=16;i<=17;i++) //pwm
{
GPIO_SetupPinMux(i,0,5);
GPIO_SetupPinOptions(i, GPIO_OUTPUT, GPIO_PUSHPULL);
}

}

2. then PWM initialization happens.

EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
// EDIS;
InitPwm1();
InitPwm2();
InitPwm3();
#ifndef SLAVE_MODE
InitPwm4();
#endif
InitPwm7();
InitPwm8();
InitPwm9();
InitPwm12();
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
// EDIS;

after completion of this event EnablePwm() function is called and during EPwmxRegs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; the PWM become high for T3 and T4.

here the pin definition happen before PWM initialization in testing_gpio_config() before EPWM initialization.

please suggest how to deal with this and make T3 and T4 to low.

0 Marlyn Rosales Castaneda20 over 3 years ago in reply to VISHAL SAPAARA

TI__Mastermind 25800 points

Hi Vishal,

By nature, this is happening because you are configuring the OUT_MODE bit. In your initial diagram you mention that you want the signals to be complementary. Can you please provide a diagram or scope capture of how you want your outputs during initialization, after calling EnablePwm(), and later in your application?

VISHAL SAPAARA said:
please suggest how to deal with this and make T3 and T4 to low.

As mentioned before, since you are using the dead-band submodule, the only way to make the outputs low is to apply a software force (TZFRC register) within the trip zone submodule to make all outputs low. When you are ready for the signals to be complementary you can clear the software force.

Best Regards,

Marlyn

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TMS320F28377D: PWM INITIALIZATION