TMS320F28035: Issue with high resolution phase shift in up direction

Hi,

I have an issue with high-resolution PWM phase-shift on the TMS320F28035. It seems to be in the wrong phase direction when configured in up direction

I want to configure PWM with a high-resolution phase shift with the following configuration:

• PWM1:
  • Counter in up-down mode
  • Fixed duty cycle = 50% (CMPA=Period/2)
• PWM2:
  • Counter in up-down mode
  • Fixed duty cycle = 50% (CMPA=Period/2)
  • High-resolution phase shift
  • Phase direction : up

With “high” phase values (e.g. phase=0.01), the phase direction is in up mode as expected. But the “small” variations of phase shift (e.g. phase=0.001) are not in up direction but are in down direction.The high-resolution phase shift always works in down direction whatever the PHSDIR register value . If I configure the phase shift direction in down mode, everything is correct.

Here is the configuration of PWM 1 & 2:

(*ePWM[n]).TBCTL.bit.PRDLD = TB_IMMEDIATE;          // set Immediate load

(*ePWM[n]).TBPRD = Period;

(*ePWM[n]).TBCTR = 0;

(*ePWM[n]).TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;

(*ePWM[n]).TBPHS.half.TBPHS = 0;

(*ePWM[n]).TBCTL.bit.PHSEN = TB_DISABLE;

(*ePWM[n]).TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;        //used to sync EPWM(n+1)

(*ePWM[n]).TBCTL.bit.HSPCLKDIV = TB_DIV1;

(*ePWM[n]).TBCTL.bit.CLKDIV = TB_DIV1;

// Counter Compare SubModule Registers

(*ePWM[n]).CMPA.half.CMPA = Period/2;               // Fix duty at 50%

// Action Qualifier SubModule Registers

(*ePWM[n]).AQCTLA.bit.CAU = AQ_SET;

(*ePWM[n]).AQCTLA.bit.CAD = AQ_CLEAR;

// DeadBand Control Register

(*ePWM[n]).DBCTL.bit.IN_MODE = DBA_ALL;

(*ePWM[n]).DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;

(*ePWM[n]).DBCTL.bit.POLSEL = DB_ACTV_HIC;          // Active Hi Complimentary

(*ePWM[n]).DBRED = 120;                              // dummy value for now

(*ePWM[n]).DBFED = 120;                              // dummy value for now

// ePWM(n+1) init.  EPWM(n+1) is a slave

//Time Base SubModule Register

(*ePWM[n+1]).TBCTL.bit.PRDLD = TB_SHADOW;

(*ePWM[n+1]).TBPRD = Period;

(*ePWM[n+1]).TBPRDHR = 0;

(*ePWM[n+1]).TBPHS.half.TBPHS = 0;                  // zero phase initially

(*ePWM[n+1]).TBPHS.half.TBPHSHR = (0<<8);           // zero phase initially

(*ePWM[n+1]).TBCTR = 0;

(*ePWM[n+1]).TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;

(*ePWM[n+1]).TBCTL.bit.PHSDIR = TB_UP;

(*ePWM[n+1]).TBCTL.bit.PHSEN = TB_ENABLE;

(*ePWM[n+1]).TBCTL.bit.SYNCOSEL = TB_SYNC_IN;       // Sync "flow through" mode

(*ePWM[n+1]).TBCTL.bit.HSPCLKDIV = TB_DIV1;

(*ePWM[n+1]).TBCTL.bit.CLKDIV = TB_DIV1;

// Counter compare submodule registers

(*ePWM[n+1]).CMPA.half.CMPA = Period/2;                    // Fix duty at 50%

(*ePWM[n+1]).CMPA.half.CMPAHR = 0;

(*ePWM[n+1]).CMPCTL.bit.SHDWAMODE = CC_SHADOW;

(*ePWM[n+1]).CMPCTL.bit.LOADAMODE = CC_CTR_PRD;

// Action Qualifier SubModule Registers

(*ePWM[n+1]).AQCTLA.bit.CAU = AQ_SET;

(*ePWM[n+1]).AQCTLA.bit.CAD = AQ_CLEAR;

(*ePWM[n+1]).DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;

(*ePWM[n+1]).DBRED = 120;                                   // dummy value for now

(*ePWM[n+1]).DBFED = 120;                                   // dummy value for now

//     Enable HiRes option

EALLOW;

(*ePWM[n+1]).HRCNFG.all = 0x0;

(*ePWM[n+1]).HRCNFG.bit.EDGMODE = HR_BEP;

(*ePWM[n+1]).HRCNFG.bit.CTLMODE = HR_PHS;

(*ePWM[n+1]).HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD;

(*ePWM[n+1]).HRPCTL.bit.HRPE = 0;

(*ePWM[n+1]).HRMSTEP = 111;

//  ePWM Type 1 can auto convert the value in CMPAHR,

//  TBPHSHR or TBPRDHR to a scaled micro-edge dealy value.

(*ePWM[n+1]).HRCNFG.bit.AUTOCONV = 1;

(*ePWM[n+1]).HRPCTL.bit.TBPHSHRLOADE = 1;

(*ePWM[n+1]).TBCTL.bit.SWFSYNC = 1;

EDIS;

Is there any mistakes in the PWM configuration?

Best regards