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TMS320F28027: High Resolution Phase Shift PWM Operation

Jeff Hensal40
Prodigy 230 points
Part Number: TMS320F28027
Other Parts Discussed in Thread: C2000WARE

Hello,

With conventional PWM operation at 500 kHz, the best phase shift granularity I can achieve between two PWM signals in the sync chain is 3° (with SYSCLKOUT = 60 MHz). For my application I need better phase shift granularity, but am having trouble getting phase shift operation to work with the High Resolution PWM.

The relevant code I have is shown below. Can someone help me achieve HRPWM phase shift and/or explain to me why this code does not work?

    EALLOW;
    SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
    EDIS;
    
    //configure ePWM1

    Uint16 period = 120;                                // 60MHz/120 = 500 kHz

    EPwm1Regs.TBPRD = period-1;                         // PWM frequency = 1 / period 
    EPwm1Regs.CMPA.half.CMPA = period/2;                // set duty 50% initially
    EPwm1Regs.CMPA.half.CMPAHR = (0 << 8);              // initialize HRPWM extension
    EPwm1Regs.TBPHS.half.TBPHS = 0;                     // initialize coarse phase to 0
    EPwm1Regs.TBCTR = 0;

    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;          // count up mode
    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;             // EPwm1 is the Master
    EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;              // set Immediate load
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

    EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;                  // High/low behavior on ePWM1
    EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;

    EALLOW;
    EPwm1Regs.HRCNFG.all = 0x0;
    EPwm1Regs.HRCNFG.bit.HRLOAD    = HR_CTR_ZERO;       // HR_CTR_ZERO_PRD;  // Load on CTR = 0 and CTR = TBPRD
    EPwm1Regs.HRCNFG.bit.AUTOCONV  = 1;                 // Enable autoconversion for HR period
    EPwm1Regs.HRCNFG.bit.EDGMODE   = HR_BEP;            // MEP control on both edges
    EPwm1Regs.HRCNFG.bit.CTLMODE   = HR_PHS;            // Selects the register (CMP/TBPRD or TBPHS) that controls the MEP:
    EPwm1Regs.HRPCTL.bit.TBPHSHRLOADE = 1;              // This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN event
    EPwm1Regs.TBCTL.bit.PHSDIR     = 1;                 // count up after SYNC event and the new value of the phase (TBPHS) is loaded.
    EPwm1Regs.HRPCTL.bit.HRPE      = 1;                 // Enable high-resolution period control.
    EDIS;

    //configure ePWM2

    EPwm2Regs.TBPRD = period-1;                          // PWM frequency = 1 / period
    EPwm2Regs.CMPA.half.CMPA = period/2;                 // set duty 50% initially
    EPwm2Regs.CMPA.half.CMPAHR = (0 << 8);               // initialize HRPWM extension
    EPwm2Regs.TBPHS.half.TBPHS = 0;
    EPwm2Regs.TBCTR = 0;

    EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
    EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;               
    EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;               // set Immediate load
    EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;           // EPwm2 is the slave
    EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
    EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;

    EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
    EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

    EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET;               
    EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;

    EALLOW;
    EPwm2Regs.HRCNFG.all = 0x0;
    EPwm2Regs.HRCNFG.bit.HRLOAD    = HR_CTR_ZERO;      //HR_CTR_ZERO_PRD;  // Load on CTR = 0 and CTR = TBPRD
    EPwm2Regs.HRCNFG.bit.AUTOCONV  = 1;                // Enable autoconversion for HR period
    EPwm2Regs.HRCNFG.bit.EDGMODE   = HR_BEP;           // MEP control on both edges
    EPwm2Regs.HRCNFG.bit.CTLMODE   = HR_PHS;           // Selects the register (CMP/TBPRD or TBPHS) that controls the MEP:
    EPwm2Regs.HRPCTL.bit.TBPHSHRLOADE = 1;             // This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN event
    EPwm2Regs.TBCTL.bit.PHSDIR     = 1;                // count up after SYNC event and the new value of the phase (TBPHS) is loaded.
    EPwm2Regs.HRPCTL.bit.HRPE      = 1;                // Enable high-resolution period control.
    EDIS;

    //set the phase registers of ePWM2
    
    EPwm2Regs.TBPHS.half.TBPHS = 119;                  // Gives a coarse phase shift from ePWM1 -> ePWM2 of 9°, or -351°
    EPwm2Regs.TBPHS.half.TBPHSHR = 100;                // Gives a fine phase shift of arbitrary value from ePWM1 -> ePWM2
	
    EALLOW;
    SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
    EDIS;

I observe with this code that ePWM1 leads ePWM2 by 9°. It works the same as if I never configured any of the HR registers at all and only used the TBPHS.half.TBPHS for phase loading. Essentially, the high resolution seems to not be working. 

Any help is sincerely appreciated. Thank you.

-Jeff  

  • 0
    TI__Expert 5940 points
    Hi Jeff,

    The TBPHSHR register's bits 7-0 are reserved, so the desired value should be left-shifted 8 bits so that it will write to bits 15-8. This is documented in the HRPWM user guide.

    Regards,
    Elizabeth
  • 0 in reply to Elizabeth Joy
    Prodigy 230 points
    Elizabeth,

    Thanks for your help. After left shifting the bits (i.e. TBPHSHR = 100 << 8), the PWM still was not HR phase shifted. I discovered that I needed to add HRMSTEP for each ePWM ( i.e. EPwm1Regs.HRMSTEP = 255) in order to set the number of MEP steps per coarse step. After adding this, the HR phase shift worked.

    However, I have a follow up question. I first set the HRMSTEP to 255 for each ePWM. I'm using 500 kHz PWM and a SYSCLOCK = 60 MHz, so each course step would be 16.67 ns. When I set the TBPHSHR to the highest value it can be, 255, the PWM experiences 35 ns phase shift, though I expect 16.67 ns. How can the maximum number of MEP steps be larger than 1 coarse step, as I have observed?

    Thanks!
    Jeff
  • 0 in reply to Jeff Hensal40
    TI__Expert 5940 points
    Hi Jeff,

    Instead of manually setting the value for HRMSTEP, you should consider using the SFO library to perform calibration that will determine the appropriate MEP scale factor and will also update the HRMSTEP register if auto conversion is enabled. There are a few HRPWM examples using the SFO library in C2000Ware (ie hrpwm_duty_sfo_v6)
    C:\ti\c2000\C2000Ware_1_00_04_00\device_support\f2802x\examples\structs\hrpwm_duty_sfo_v6

    The SFO library usage is also documented in the HRPWM user guide.

    Regards,
    Elizabeth