TMS320F28027: High Resolution Phase Control Mode Issues

Armani,

Setting TBPHSHR only configures the High-resolution extension. If you want to phase shift 120 degrees you will need to configure TBPHS to the closest value then use TBPHSHR, which has a step size on the order of 180pS, to shift the rest of the way.

Regards,
Cody

Cody,

So I did as you said and configured TBPHS as I usually would and then used TBPHSHR to shift the rest of the way, but I do not see any impact in the phase from TBPHSHR. Am I using the correct syntax to configure and utilize TBPHSHR?

Code Start:

--------------------------------------------------------------------------

void

InitEPwm1Example()

{

EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD; // Period = 900 TBCLK counts

EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero

EPwm1Regs.TBPHS.half.TBPHSHR = 0; // Set Phase register to zero

EPwm1Regs.TBCTR = 0x0000; // Clear counter

EPwm1Regs.CMPA.half.CMPA = EPWM1_MIN_CMPA; // Set compare A value

EPwm1Regs.CMPB = EPWM1_MIN_CMPB; // Set Compare B value

// was not here prior to 3/31

EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT -- > TBCLK = SYSCLKOUT = 60 MHz

EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode

EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module

EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;

EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module

EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;

EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero

EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero

EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM1A

EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;

// was not here prior to 3/31

EPwm1Regs.AQCTLB.bit.CBU = AQ_SET; // Set PWM1B on event B, up count

EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR; // Clear PWM1B on event B, down count

// HRPWM Code

EALLOW; // Note these registers are protected

// and act only on ChA

EPwm1Regs.HRCNFG.all = 0x0; // clear all bits first

EPwm1Regs.HRCNFG.bit.AUTOCONV = 1; // Enable autoconversion for HR period

EPwm1Regs.HRPCTL.bit.TBPHSHRLOADE = 1; // This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN, TBCTL[SWFSYNC] or digital compare event

EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; // Shadow load on CTR=Zero

EPwm1Regs.HRCNFG.bit.EDGMODE = HR_BEP; // Control Both Edge Position

EPwm1Regs.HRCNFG.bit.CTLMODE = HR_PHS; // PHSHR controls the MEP

EDIS;

}

//

// InitEPwm2Example -

//

void

InitEPwm2Example()

{

EPwm2Regs.TBPRD = EPWM2_TIMER_TBPRD; // Period = 900 TBCLK counts

EPwm2Regs.TBPHS.half.TBPHS = 58;

EPwm2Regs.TBPHS.half.TBPHSHR = (100 << 8);

EPwm2Regs.TBCTR = 0x0000; // Clear counter

EPwm2Regs.CMPA.half.CMPA = EPWM2_MIN_CMPA; // Set compare A value

EPwm2Regs.CMPB = EPWM2_MIN_CMPB; // Set Compare B value

EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT -- > TBCLK = SYSCLKOUT = 60 MHz

EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode

EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Master module

EPwm2Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count DOWN on sync (=120 deg)

EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;

EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync down-stream module

EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;

EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero

EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero

EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM1A

EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;

// was not here prior to 3/31

EPwm2Regs.AQCTLB.bit.CBU = AQ_SET; // Set PWM1B on event B, up count

EPwm2Regs.AQCTLB.bit.CBD = AQ_CLEAR; // Clear PWM1B on event B, down count

// HRPWM Code

EALLOW; // Note these registers are protected

// and act only on ChA

EPwm2Regs.HRCNFG.all = 0x0; // clear all bits first

EPwm2Regs.HRCNFG.bit.AUTOCONV = 1; // Enable autoconversion for HR period

EPwm2Regs.HRPCTL.bit.TBPHSHRLOADE = 1; // This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN, TBCTL[SWFSYNC] or digital compare event

EPwm2Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; // Shadow load on CTR=Zero

EPwm2Regs.HRCNFG.bit.EDGMODE = HR_BEP; // Control Both Edge Position

EPwm2Regs.HRCNFG.bit.CTLMODE = HR_PHS; // PHSHR controls the MEP

EDIS;

}

Actually I was able to figure out that I was missing EPwm1Regs.HRMSTEP = 255; declaration for each register. My questions now are the following:

1) How do I select an HRMSTEP value? (Without using SFO - I attempted this and could not get my code to run)

2) Is the max MEP Steps Per the F28027 with a 60MHz clock 93? If so, what does setting HRMSTEP = 255 do?

3) Is a coarse step with a 60MHz clock equal to 150 pS (what it says in the guide I am reading http://www.ti.com/lit/ug/spru924f/spru924f.pdf) or is it 180pS like you said above?

4) Can I take the decimal portion of my calculated TBPHS (say it is 58.589 so the decimal would be 0.589), and multiply this by something to set TBPHSHR to my desired phase shift?

I really appreciate your help.

Armani,

1. You will need to run the SFO, it is what calibrates the HRPWM module. The HRPWM examples should show this off.
2. No, it depends device to device.
3. a course step with a 60MHz clock is equal to 1/60MHz. IE. a course step is just one clock pulse width. The HR portion of the PWM are ~180pS per MEP step.
4. Yeah, that's about how it works when you are using auto convert, that should be detailed in the documentation and examples.

Regards,
Cody

Thanks Cody.

Do you have any documentation or examples for reference that show TBPHSHR being set and have SFO being used? I have not had any luck finding examples with High Resolution Phase Control being used.

Best,

Armani