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TMS320F28075: ADCSOC pulse to the CLB using the CLB XBAR

Leelakrishna Jonnadula
Prodigy 35 points
Part Number: TMS320F28075
Other Parts Discussed in Thread: SYSCONFIG

Hi,

I am looking for the ways to have division by 16 for soc period. looks like ETSOCPS[SOCAPRD2] is limited to 15. I just need one more count :( .  I got to know we could achieve 16th period by redirecting ADCSOC pulse to the CLB using the CLB XBAR and configure CLB to increment a counter with period 16 and send out a pulse to a GPIO via CLB OUTPUT XBAR on every 16th ADCSOC pulse. Could anyone help me with the code to achieve this requirement? I am not familiar with coding CLB.

Thanks,

Leela

  • 0
    TI__Genius 17521 points

    Hi Leela,

    Thank you for reaching out on the E2E forums. The CLB module is configured using the CLB Tool found in our SysConfig development tool. For exactly how to use this tool, I would refer you to look at the CLB lab activity in C2000 Academy (https://dev.ti.com/tirex/global?id=c2000Academy) which gives a step-by-step overviewing of configuring the CLB. 

    In regards to your specific implementation, this is what I would do: 

    ADCSOCA signal is available on MUX13 of the CLBXBAR, route this signal to an AUXSIG. That AUXSIG value can be configured as a CLB input by choosing this AUXSIG from global input mux, with rising edge input filtering. On CLB counter, choose this BOUNDARY input as the enable (when to count) for the counter and configure it to reset on value 16 (assign to match_1 and configure reset as match_1). This COUNTER.match_1 can be configured as an input into one of the OUTPUT LUTs (need to use either 4 or 5 if wanting to route out to a GPIO). Then choose appropriate MUX from OUTPUTXBAR that maps to CLB OUT4 or OUT5

    Please let me know if you have any other questions!

    Regards,

    Peter