TMS320F28388D: Weird behavior of the CLB with the CLB Output XBar

Tool/software:

Hello,

I’m experiencing unexpected behavior when generating clock signals with the CLB and routing them to GPIOs via the CLB Output Xbars.

Setup

• I’m generating two clocks and routing them to GPIOs using the CLB Output Xbars.
• An Input Xbar enables the CLB counters.
• My goal is to keep the GPIOs high except when generating a clock signal.

Observed Behavior

• With both clock signals inverted: GPIOs start high. When counters start, the CLB generates the clocks as expected. However, when the counters stop, both GPIOs stay low.
• Without inversion: GPIOs start low. The clocks are generated correctly when counters start, but after stopping, both GPIOs stay low.
• Inverting only one clock signal: The inverted GPIO starts high, and the other starts low. During repeated starts and stops, one GPIO remains high, and the other low, but this alternates unpredictably.

The CLB Logic Control Register (CLB_DBG_OUT) reflects this behavior, indicating a correlation between the CLB Output Xbar invert mode and the CLB outputs, which I hadn’t anticipated.

Any insights on this correlation would be greatly appreciated.

Regards,

Wilko