TMS320F280039C: Bootloader SPI Slave Missing First Bit on Some Hardware

Derek Cook

Part Number: TMS320F280039C

Hello,

I have an annoying problem because my bootloader works very well most of the time. However, I have some hardware that when used misses the first bit from the master. All of the hardware is the same, just different cards.

My bootloader is set up with a SPI slave config, below is the SPI config code and my RX and TX interrupts:

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void SPI_Init()
{
    Interrupt_register(INT_SPIA_RX, &spiaRxFIFOISR);
    Interrupt_register(INT_SPIA_TX, &spiaTxFIFOISR);//TX
    //SPIA_slave initialization
    SPI_disableModule(REPA_DSPI_SLAVE_BASEADDR);
    SPI_setConfig(REPA_DSPI_SLAVE_BASEADDR, DEVICE_LSPCLK_FREQ, SPI_PROT_POL0PHA0,
                  SPI_MODE_SLAVE, 500000, 8);
    SPI_enableFIFO(REPA_DSPI_SLAVE_BASEADDR);
    SPI_setFIFOInterruptLevel(REPA_DSPI_SLAVE_BASEADDR, SPI_FIFO_TXEMPTY, SPI_FIFO_RX8);
    SPI_clearInterruptStatus(REPA_DSPI_SLAVE_BASEADDR, SPI_INT_TXFF);//TX
    SPI_clearInterruptStatus(REPA_DSPI_SLAVE_BASEADDR, SPI_INT_RXFF);
    SPI_clearInterruptStatus(REPA_DSPI_SLAVE_BASEADDR, SPI_INT_RXFF_OVERFLOW);
    SPI_clearInterruptStatus(REPA_DSPI_SLAVE_BASEADDR, SPI_INT_RX_OVERRUN);
    SPI_clearInterruptStatus(REPA_DSPI_SLAVE_BASEADDR, SPI_INT_RX_DATA_TX_EMPTY);
    SPI_enableInterrupt(REPA_DSPI_SLAVE_BASEADDR, SPI_INT_RXFF);
    SPI_enableInterrupt(REPA_DSPI_SLAVE_BASEADDR, SPI_INT_TXFF);//TX
    SPI_disableLoopback(REPA_DSPI_SLAVE_BASEADDR);
    SPI_setEmulationMode(REPA_DSPI_SLAVE_BASEADDR, SPI_EMULATION_FREE_RUN);
    SPI_enableModule(REPA_DSPI_SLAVE_BASEADDR);
    Interrupt_enable(INT_SPIA_TX);//TX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

void SPI_Init()
{
    Interrupt_register(INT_SPIA_RX, &spiaRxFIFOISR);
    Interrupt_register(INT_SPIA_TX, &spiaTxFIFOISR);//TX
    //SPIA_slave initialization
    SPI_disableModule(REPA_DSPI_SLAVE_BASEADDR);
    SPI_setConfig(REPA_DSPI_SLAVE_BASEADDR, DEVICE_LSPCLK_FREQ, SPI_PROT_POL0PHA0,
                  SPI_MODE_SLAVE, 500000, 8);
    SPI_enableFIFO(REPA_DSPI_SLAVE_BASEADDR);
    SPI_setFIFOInterruptLevel(REPA_DSPI_SLAVE_BASEADDR, SPI_FIFO_TXEMPTY, SPI_FIFO_RX8);
    SPI_clearInterruptStatus(REPA_DSPI_SLAVE_BASEADDR, SPI_INT_TXFF);//TX
    SPI_clearInterruptStatus(REPA_DSPI_SLAVE_BASEADDR, SPI_INT_RXFF);
    SPI_clearInterruptStatus(REPA_DSPI_SLAVE_BASEADDR, SPI_INT_RXFF_OVERFLOW);
    SPI_clearInterruptStatus(REPA_DSPI_SLAVE_BASEADDR, SPI_INT_RX_OVERRUN);
    SPI_clearInterruptStatus(REPA_DSPI_SLAVE_BASEADDR, SPI_INT_RX_DATA_TX_EMPTY);
    SPI_enableInterrupt(REPA_DSPI_SLAVE_BASEADDR, SPI_INT_RXFF);
    SPI_enableInterrupt(REPA_DSPI_SLAVE_BASEADDR, SPI_INT_TXFF);//TX
    SPI_disableLoopback(REPA_DSPI_SLAVE_BASEADDR);
    SPI_setEmulationMode(REPA_DSPI_SLAVE_BASEADDR, SPI_EMULATION_FREE_RUN);
    SPI_enableModule(REPA_DSPI_SLAVE_BASEADDR);
    Interrupt_enable(INT_SPIA_TX);//TX
    Interrupt_enable(INT_SPIA_RX);

}

__interrupt void spiaTxFIFOISR(void)
{
    uint16_t i,SendingByte;

    for(i = 0; i < 8; i++)
    {
        //SPI_writeDataNonBlocking(REPA_DSPI_SLAVE_BASEADDR, sBuffer[sbufferindex]);
        if(NumnberOfDatatoSend>0){
            if(sbufferindex ==90){
                SendingByte = sBuffer[90]<<9 | ((sBuffer[0] & 0x80)<<1);
                sBuffer[90] = 0;
                sbufferindex = 0;
            }else{
                SendingByte = sBuffer[sbufferindex]<<9 | ((sBuffer[sbufferindex+1] & 0x80)<<1);
                sBuffer[sbufferindex]=0;
                sbufferindex++;
            }
            //SendingByte = sBuffer[sbufferindex++]<<8;
            //if(sbufferindex==90)sbufferindex =0;
            SPI_writeDataNonBlocking(REPA_DSPI_SLAVE_BASEADDR, SendingByte);
            NumnberOfDatatoSend--;
        }
        else
            SPI_writeDataNonBlocking(REPA_DSPI_SLAVE_BASEADDR, 0);

    }
//    printf("running");
    SPI_clearInterruptStatus(REPA_DSPI_SLAVE_BASEADDR, SPI_INT_TXFF);
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP6);
}

__interrupt void spiaRxFIFOISR(void)
{

    uint16_t i,reByte;
    uint16_t SendingByte;


//    if(dataRecieved){
//        SPI_clearInterruptStatus(REPA_DSPI_SLAVE_BASEADDR, SPI_INT_RXFF);
//        Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP6);
//    }

    for(i = 0; i < 8; i++)
//    while(SPI_getTxFIFOStatus(REPA_DSPI_SLAVE_BASEADDR) != SPI_FIFO_RXEMPTY)
    {
    reByte = SPI_readDataNonBlocking(REPA_DSPI_SLAVE_BASEADDR) & 0xFF;
    if (/*!dataRecieved && */(bufferindex !=0 || ((reByte & 0xFF) == 0x5A)))
        buffer[(bufferindex++ % 300)] =reByte ;
    }



    datalen = buffer[2] & 0xff;
    //datalen |= (buffer[3] <<8) & 0xff00;
    PacketsRecv = datalen + 6;
    if(datalen == 0 && (buffer[1] == 0xA6 || buffer[1] == 0xA1 || buffer[1] == 0xA2)) {
        datalen=2;
        PacketsRecv=2;
        dataRecieved=true;
       // SPI_clearInterruptStatus(REPA_DSPI_SLAVE_BASEADDR, SPI_INT_RXFF);
    }else if(bufferindex > 5 && bufferindex >= PacketsRecv){
        dataRecieved=true;
        //SPI_clearInterruptStatus(REPA_DSPI_SLAVE_BASEADDR, SPI_INT_RXFF);
    }

    SPI_clearInterruptStatus(REPA_DSPI_SLAVE_BASEADDR, SPI_INT_RXFF);
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP6);
}

My master is sending 0x5A 0xA6 to ping the bootloader, the bootloader is seeing consistently 0x5A 0x26 on the hardware that does not work with the bootloader. This means I am missing bit 7 of the 2nd byte. What is interesting, is that if I change the protocol parameter in SPI_setConfig() to SPI_PROT_POL0PHA1 (Mode 1. Polarity 0, phase 1. Rising edge with delay.) or SPI_PROT_POL1PHA0(Mode 2. Polarity 1, phase 0. Falling edge without delay.) from SPI_PROT_POL0PHA0 (Mode 0. Polarity 0, phase 0. Rising edge without delay.) this fixes the read issue when using this hardware. However, the TX to the master then does not work.

What would you recommend checking here? I have the bootloader working well on 4 systems but I have 1 system and 1 card where the bootloader is missing bits. However, if I download the SPI application firmware to the board via XDS110 then the SPI works fine and does not miss bits.

Thanks for the help!

over 2 years ago

0 Santosh Jha over 2 years ago

TI__Guru 50531 points

Hi,

Due to Thanksgiving Holiday, the subject matter expert is out of office. We will get back to you next week.

Thanks & Regards,
Santosh

0 Manoj Santha Mohan over 2 years ago

TI__Guru 55700 points

This looks like board artifact. Did you check SPI pins on oscilloscope and see whether first bit is delayed because of board artifact ( capacitance can delay rise time/ fall time). You can try enabling pull-up resistor to see whether that fixes the issue. Check how long are the traces? If the trace length is too long it can cause this behavior.

+1 Derek Cook over 2 years ago in reply to Manoj Santha Mohan

Intellectual 880 points

Hi Manoj,

My data changes on the falling edge of the clock, not the rising edge. Fixing the protocol fixed my issue. Thanks for the help!

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TMS320F280039C: Bootloader SPI Slave Missing First Bit on Some Hardware