SPRUIN7A - TMS320F28002x Technical Reference Manual (Rev. A)
Section 17.8.2 Operational Highlights for the PWM Chopper Submodule - mentions "The carrier clock is derived from
EPWMCLK. Its frequency and duty cycle are controlled via the CHPFREQ and CHPDUTY bits in the PCCTL
However, from the explanation of the register field description for CHPFREQ bits, it appears like the chopping frequency is derived by dividing TBCLK (instead of EPWMCLK as mentioned in 17.8.2).
Can you please clarify?