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TMS320F280025C: PWM chopper frequency

Part Number: TMS320F280025C


SPRUIN7A - TMS320F28002x Technical Reference Manual (Rev. A)

Section 17.8.2 Operational Highlights for the PWM Chopper Submodule - mentions "The carrier clock is derived from
EPWMCLK. Its frequency and duty cycle are controlled via the CHPFREQ and CHPDUTY bits in the PCCTL
register. "

However, from the explanation of the register field description for CHPFREQ bits, it appears like the chopping frequency is derived by dividing TBCLK (instead of EPWMCLK as mentioned in 17.8.2).

Can you please clarify?


With regards,


  • Hi Vijay,

    The entry in the register field description is most likely assuming that TBCLK is equal to EPWMCLK, meaning the diagram would be correct in indicating that PSCLK is derived from EPWMCLK directly. I will try to find more information as soon as possible to confirm this.

    Thank you,


  • Hi Vijay,

    I did some testing by altering the TBCLK divider while leaving the chopper clock dividers constant, which resulted in a different number of pulses produced by the chopper module. This would indicate the chopping frequency is independent of the TBCLK frequency and derived from EPWMCLK.

    I will look into updating our documentation to make this more clear.

    Thank you,