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TMS320F280041-Q1: some questions about PLL and clock sources

Will Gao
Intellectual 2335 points
Part Number: TMS320F280041-Q1

Hi BU experts, 

Customer asks me some questions, and need your help: 

1). If the VCOCLK in the PLL circuit does not meet the spec requirement shown in the datasheet, what will happen? According to customer's configuration, the f(VCO) would be 100M. They want to know the risk of this configuration. 

2). If f(VCO) < 120MHz, may the PLL be bypassed by device itself automatically, just like Missing Clock Detection mechanism, and application not know? 

Regards, 

Will 

  • 0
    TI__Guru* 95315 points

    Will,

              Customer must adhere to the datasheet spec and not operate the PLL outside of the datasheet spec. If SYSCLK of 100 MHz is desired, PLL output must be 200 MHz and a divider of /2 must be used. Operating the PLL without a divider may cause duty-cycle issues and lead to unpredictable device behavior.

    Will Gao said:
    2). If f(VCO) < 120MHz, may the PLL be bypassed by device itself automatically, just like Missing Clock Detection mechanism, and application not know? 

    No, no such mechanism exists for automatic detection and bypassing.

  • 0 in reply to Hareesh Janakiraman
    TI__Intellectual 2335 points

    What is the duty-cycle issues and the unpredictable device behavior exactly? 

    Br, Will 

  • +1 in reply to Will Gao
    TI__Guru* 95315 points

    Will,

                  Duty cycle may not be 50%. It is not possible to precisely identify what would happen when the PLL is operated outside of its specifications. That is why I used the word “unpredictable”. Please advise customer to operate the PLL within the datasheet spec.