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TMS320F28030: When an instruction with an empty address (or an address with invalid information) is executed on the non-interrupt processing side

Part Number: TMS320F28030

I am asked following questions by customer. Please review and answer for each questions.

【situation】
In this device, non-interrupting processing is permanently executed in a while loop, while another processing is periodically executed by a timer interrupt.
It has been confirmed that there is some kind of anomaly while using the application equipped with this device, and that it is in the following state.
・It is presumed that non-interrupt processing cannot be executed.
・Timer interrupt processing is executed correctly in terms of cycle and processing content.

【question】 How does the device behave when an instruction with an empty address (or an address with invalid information) is executed on the non-interrupt side? ・Whether a reset or a jump to exception handling occurs ・(When no reset or jump occurs) How does the non-interrupt processing side proceed with instruction execution after the above? ・Whether timer interrupt processing occurs after the above
  • How does the device behave when an instruction with an empty address (or an address with invalid information) is executed on the non-interrupt side?

    Any unimplemented opcode would trigger an ITRAP, the ISR for which is in boot-ROM. What happens next is determined by whether the watchdog is enabled. If WD is disabled, the timer ISR will be executed as needed. If WD is enabled, it's counter would overflow and reset the device.