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TMS320F280039C: F280039C SCI Break character

ahugron hugron
Intellectual 320 points
Part Number: TMS320F280039C

Hi,

I am using a SCI in address mode and I try to detect a BRKDT character sent by a different device (Slave). The BRKDT in SCIRXST does not set to be set even if I short the RX line to ground times to times. Simulate BRK.

What are exact condition for the break character bit to be set. According to spec, it has to be at least 9.625 bits. Is there a maximum? My other device is sending 13 bits at 0. (I am using 8 bits data + address mode (no parity).

- What is the difference compare to frame error (FE bits)? Is it also set even if data is 0?

- If I get a BRKDT detected, is RXRDY bit set also with the corresponding RX buffer (SCIRXBUF) at 0?

Thanks,


Arnaud

  • 0
    TI__Mastermind 23290 points

    Hi Arnaud,

    Can you verify that the SCICTL1.SLEEP bit is not set? This is the only scenario I am aware of where the BRKDT bit would not be set even if the RX line is held low?

    I will need some time to look into your other questions, please expect a response back by tomorrow.

    Thank you,

    Luke

  • 0 in reply to Luke Jones
    Intellectual 320 points

    See attached SCI registers. I am continuously sending from a different MCU to RX pin a break character every 300ms but the BRKDT is never set.

    RXRDY or FE is also not set. when receiving this Break character or when shorting and releasing RX line.

    Thanks

  • 0 in reply to ahugron hugron
    TI__Mastermind 23290 points

    Hi Arnaud,

    Does the issue when sending a break detect character occur all the time or only periodically? If you send me your configuration code and a scope shot of your RX line when encountering the issue that will help to debug this.

    To answer your second and third question from your original post,

    If break detect is set, RXRDY will not become set.

    Frame error is different from break detect in that it relies on the SCI to not be in sleep mode and a missing stop bit needs to be detected. After a missing stop bit is detected(the stop bit alone is corrupted) and frame error is set, the RX line needs to be held low for an additional 10 cycles for a break detect to occur. It's possible you are not seeing the break detect because SCI RX is only held low for 13 cycles.