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TMS320F280039C: SCI break usage for M-CRPS DSSI

Wayne Huang
Genius 15745 points
Part Number: TMS320F280039C
Other Parts Discussed in Thread: C2000WARE

Dear Champs,

I am asking this for our customer.

In the latest M-CRPS standard for server PSU, there is DSSI using UART like below.

http://files.opencompute.org/oc/public.php?service=files&t=bf2e242598f9f5a9d0dcd899849e5608

The standards says it uses 11-bit LOW as break for configuration.

In F28003x TRM, it says, break detection is LOW for 9.625 bits

Questions:

1. Can SCI module be used for detecting 11-bits LOW for M-CRPS standard? It seems it will go into an interrupt for 9.625 bits LOW? Do you have any comment?

2. Do we have any break detection based interrupt example for the user?

  • 0
    TI__Mastermind 23990 points

    Hi Wayne,

    1. Unfortunately the 9.625 low bits to trigger a break detect is fixed and cannot be increased to 11.

    2. We don't have an example demonstrating break detect based interrupts specifically, but the receive and break detect events share the same interrupt vector. sci example 2 in c2000ware demonstrates an example of receive interrupts. To modify this to check for break detects, the user should check the BRKDT flag at the beginning of their ISR to check if it was a break detect that triggered the interrupt. As long as RXBKINTENA is enabled, either a frame received event or a break detect will trigger this interrupt.