TMS320F28377D: 16-bits access to 32-bits asynchronous device through EMIF

Could you send (privately) the connections between the MCU and your asynch device? You may also want to look at this post. In the interim, I'll request a software expert for inputs. 

Please, could you send me the procedure to send you private data.

Thanks

I have sent you a friendship request. Once you accept it, you will be able to send messages to me privately.

You have not provided the schematics but only shown the connection like a block diagram, so it is not possible to identify the SRAM chip that you are using.  Please refer to the attached schematic that shows the connection to a 16-bit SRAM chip. The schematic can be downloaded from C:\ti\c2000\C2000Ware_4_03_00_00\boards\TIDesigns\F28379D_EMIF_DC.

Please clarify the absence of byte enable connection (DQM pins).

F28379D_EMIF_DC_SCH.pdf

Hello,

The 32-bits asynchronous device is a FPGA.

1) Is it mandatory to use the byte enable ?

2) Is it the solution to the dublication of the 16-bits data on the 32-bits databus ?

3) What are the impacts on the exchange speed  between CPU and FPGA  if byte enable is used or not ?

4) If the byte enable is not used, how to guarantee that the compiler performs only 32-bits accesses ?

Ex:

*Ptr32 = * Ptr32 | (uint32_t) 0xAAAAFFFF;
is traduced by:
OR *+XAR2[0],#65535
OR *+XAR2[1],#43690
These assembler instructions are instructions which manage only 16-bits data and the result is consequently wrong because of the duplication on the 32-bits databus.

Thanks

Best regards.

Please acept some delay in response due to the July 4th holiday in the US. Please send the schematics (privately) of every connection between the MCU and FPGA .

Hi,

I have already sent a diagram (in a private message) with the indication of all pins for the EMIF.
For the FPGA, the pins have a general purpose. It could be used as data, address, write enable, etc...
Consequently, the schematic will not give you more information than the diagram.
Furthermore, I sent the configuration of the GPIO and the EMIF.

For your information, in our tests, we can see with a scope that, during the write access, the most significant bit is set to 1 (due to the duplication of the 16-bits LSB on the 16-bits MSB) instead of being kept to 0.

Best regards.