TMS320F280049C: C2000Ware v4 uses 24 cycles instead of 60 cycles for PLL turn off

Hi Jose,

I am able to see the 60 clock cycles delay in the f28004x_sysctl.c file (C2000Ware_4_01_00_00\device_support\f28004x\common\source\f28004x_sysctrl.c).

        //

        // Bypass PLL and set dividers to /1

        //

        ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0;

        //

        // Delay of at least 60 OSCCLK cycles required post PLL bypass

        //

        asm(" RPT #60 || NOP");

        ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 0;

As per the SysCtl_delay(3U); function it would be (3*5) + 9 cycle overhead = 24 cycles.

I will get back to you on this.

Please have a look at similar topic - (+) TMS320F280049C: DriverLib PLL Configuration Delay - C2000 microcontrollers forum - C2000︎ microcontrollers - TI E2E support forums

Thanks

Aswin 

Hello Aswin,

I can see the same code as you do in the path you mention.  The path for the code we were using as a reference for our code and this post is in:

C:\ti\c2000\C2000Ware_4_01_00_00\driverlib\f28004x\driverlib\sysctl.c

Is there any reason why the two would be different?

Thanks!