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TMS320F28379D: Taking FFT of a periodic signal having samples not exact multiple of 2.

Part Number: TMS320F28379D
Other Parts Discussed in Thread: C2000WARE, TIDM-THREEPHASEMETER-F67641, CD4040B

We want to accurately calculate the harmonics in the grid voltage up to 9th harmonic. The sampling is being done at a fixed rate of 16KHz i.e. the rate at which PWMs frequency is set.  At exactly 50 Hz this will result is 320 sample points. Similarly at 60Hz it will result in approx. 267 samples. Furthermore since the grid frequency can vary so the number of sample points per cycle can vary. I am totally clue less about a good solution to this problem as the FFT libraries compute on the samples that are 2^N only. The sampled signal segment must contain a whole number of periods. I understand if FFT is computed on incomplete cycle (for e.g. 256/320=0.8 portion of 50Hz cycle or 512/320=1.6 portion of 50Hz cycle) then this results in a lot of other harmonics in the result and incorrect results. Please guide about how to proceed about this. 

  • Hello Asad,

    If you intend to use the FFT library, which is optimized for computational efficiency, then there must be 2^N points. Otherwise, you will have to implement your own solution. You can look at an example like this:

    https://lloydrochester.com/post/c/example-fft/#:~:text=more%20usage%20examples.-,C%20Header%20of%20the%20FFT,signals%20are%20put%20through%20rearrange%20.

    Keep in mind that the FFT libraries used in C2000Ware are optimized to be fast, so there will be a tradeoff for accuracy if your data does not meet the 2^N requirement. If you want accuracy, implementing your own FFT function will work but you will lose the speed advantage. This will be up to you to determine which one is best for your use case.

    Best regards,

    Omer Amir

  • Hi Omer Amir,

       Assuming a vary ideal sampling frequency of say 1.6 KHz for a 50 Hz signal. At this very ideal case we can have 1600/50= 32 samples. Now if there is a variation of +/- 1 Hz then the number of samples per cycle can be 31 or 33 i.e. not multiple of 2. Now if the same system needs to measure for 60 Hz then it will imply usual samples to be 1600/60=27 samples. So practically it is very less likely that the actual grid can have a multiple of 2 samples for any fixed sampling frequency. Also the frequency bin in this case will be 1600/27= 59.26 Hz i.e. not exact multiples of 60. Calculating twiddle factors on the go every time will be computationally very expensive. There are two problems:

    1- Equally spaced samples in a complete cycle to be exact multiple of 2 is not necessarily the case while doing calculations for the twiddle factors per cycle will be computationally very expensive.

    2- Sampling at fixed rate does not guarantee the frequency bins at exact multiple of fundamental.

    I think that TI will have some good solution to this problem since it is not a very rare implementations. I believe that many people would have already done calculations for the grid harmonic calculations with some good accuracy.  There is something very basic that I may be missing out. Does TI provides any application note or any example implementation for this use case?. I was searching but could only find TIDM-THREEPHASEMETER-F67641 as a relevant source. They use Goertzel algorithm for THD calculation. Can you comment on its usage for my application?.

  • Asad,
    a common solution to this problem is to use some kind of PLL that assures synchronous sampling. This is also mandated in the power quality analyzer's standard IEC 61000-4-30.
    You can drive the ADC directly with the PLL like HC4046 or indirectly by recreating the clock with some kind of variable frequency PWM that follows mains frequency.

    Regards,
    Andy

  • Hi Andy,

       Can you refer to any application note or sample implementation for the methods that you have mentioned. In-fact we explored the PLL (SN74LV4046ANSR) option with the multiplier IC (CD4040B) to take exactly 32 samples in a cycle of the grid voltage. However the results of FFT from this sampled data are not accurate. Particularly we find more errors in the second harmonic and third harmonic calculations. We understand that this is due to some jitter in the PLL causing the sampling pulses not to be exactly equal distant. It will be very helpful if we have some reference implementation to see if we are doing something wrong. The second method of variable PWM following mains frequency is something new for us. Any further details on this topic will also be helpful.

  • The second method is based on measuring mains frequency in a cycle-by-cycle basis, or even better halfcycle-by-halfcycle, with, for example, one of the eCAPs. Then, each cycle or half cycle the PWM frequency is updated with the new value. The advantage of this method is that you can filter out unwanted frequency changes or manage the situations when the mains voltage has some dips or interruptions. If your PWM cannot generate high frequency needed to drive ADC clock with enough precision you will need to use the PLL anyway (PLL driven by low frequency PWM).
    But in both methods the most important is to get the mains frequency accurately - this means that you have to get rid of the harmonics before you can measure the frequency. One possible method is to implement passband analog filter, e.g. 40-70Hz.

    Regards,
    Andy

  • Hi Asad,

    May I know the application and is the 16kHz PWM frequency spec coming from any power converter ISR. Also are you using internal ADC or external.

    You can find the documentation on C2000 FFT libraries at C:\ti\c2000\C2000Ware_5_00_00_00\libraries\dsp -> docs folder

    Thanks and regards, Pawan

  • Hi Pawan Nayak,

            The application is grid tied solar power converter. You are correct that 16KHz is the switching frequency of the inverter switches. We are using the internal ADC.  For the FFT we are using external ADC trigger coming from a PLL circuit tuned to grid frequency. We have been using only 32 points sampling so far and think that it was too small number and one of the reason for THD measurement inaccuracy besides the inherent jitter in the PLL output. Now we have increased the sampling to 128 points per cycle and testing with it. We are hopeful for the improvement.

    Thanks & regards.

  • Hi Asad,

    Keep us posted if further support needed on this one. We have a software PLL library available in case you would like to try out software based PLL.

    Thanks and regards, Pawan

  • Hi Pawan Nayak,

        The results are much better after we have increased the sampling to 128 points. However we are having some hard time tuning the PLL to lock from 45 Hz to 65 Hz grid frequency range ( The inverter can operate on both 50 Hz grid as well as 60 Hz grid). We can give software PLL a try since it will be easily reconfigurable for 50Hz/60Hz and attractive from point of view of hardware cost reduction as well. Please share some details and related application note/example.

  • Hi Asad,

    You can find the software PLL library at C:\ti\c2000\C2000Ware_DigitalPower_SDK_4_04_00_00\libraries\spll\include

    The related documentation is available at Modules

    The application notes for both single phase and 3 phase software PLL's are below

    https://www.ti.com/lit/an/sprabt4a/sprabt4a.pdf

    https://www.ti.com/lit/an/sprabt3a/sprabt3a.pdf

    Thanks and regards, Pawan

  • The results are acceptable with 128 point FFT. It appears that 32 point sampling was not good enough. I think that we can close this ticket.