TMS320F28377D: ADC ISR ADCA1_INT Cannot be Triggered after 28543 cycle

Alvin

Prodigy 130 points

Part Number: TMS320F28377D

Hi expert,

This problem probably happened 1 time of 500 times startup. there is only this one interrupts in my project.

Setup are as following:

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acqps = 28; //75ns
    EALLOW;
    AdcaRegs.ADCSOC0CTL.bit.CHSEL  = 1;  //SOC0 will convert on channel 1 
    AdcaRegs.ADCSOC1CTL.bit.CHSEL  = 4;  //SOC1 will convert on channel 4 
    AdcaRegs.ADCSOC2CTL.bit.CHSEL  = 3;  //SOC2 will convert on channel 3 
    AdcaRegs.ADCSOC3CTL.bit.CHSEL  = 2;  //SOC3 will convert on channel 2 
    AdcaRegs.ADCSOC4CTL.bit.CHSEL  = 5;  //SOC4 will convert on channel 5 
    AdcaRegs.ADCSOC0CTL.bit.ACQPS  = acqps; //sample is acqps + 1 SYSCLK cycles
    AdcaRegs.ADCSOC1CTL.bit.ACQPS  = acqps; //sample is acqps + 1 SYSCLK cycles
    AdcaRegs.ADCSOC2CTL.bit.ACQPS  = acqps; //sample is acqps + 1 SYSCLK cycles
    AdcaRegs.ADCSOC3CTL.bit.ACQPS  = acqps; //sample is acqps + 1 SYSCLK cycles
    AdcaRegs.ADCSOC4CTL.bit.ACQPS  = acqps; //sample is acqps + 1 SYSCLK cycles
    AdcaRegs.ADCSOC5CTL.bit.ACQPS  = acqps; //sample is acqps + 1 SYSCLK cycles
    AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT1 flag
    AdcaRegs.ADCINTSEL1N2.bit.INT2E = 1; //enable INT2 flag
    AdcaRegs.ADCINTSEL3N4.bit.INT3E = 0; //disable INT3 flag
    AdcaRegs.ADCINTSEL3N4.bit.INT4E = 0; //disable INT4 flag
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

acqps = 28; //75ns

    EALLOW;
    AdcaRegs.ADCSOC0CTL.bit.CHSEL  = 1;  //SOC0 will convert on channel 1 
    AdcaRegs.ADCSOC1CTL.bit.CHSEL  = 4;  //SOC1 will convert on channel 4 
    AdcaRegs.ADCSOC2CTL.bit.CHSEL  = 3;  //SOC2 will convert on channel 3 
    AdcaRegs.ADCSOC3CTL.bit.CHSEL  = 2;  //SOC3 will convert on channel 2 
    AdcaRegs.ADCSOC4CTL.bit.CHSEL  = 5;  //SOC4 will convert on channel 5 

    AdcaRegs.ADCSOC0CTL.bit.ACQPS  = acqps; //sample is acqps + 1 SYSCLK cycles
    AdcaRegs.ADCSOC1CTL.bit.ACQPS  = acqps; //sample is acqps + 1 SYSCLK cycles
    AdcaRegs.ADCSOC2CTL.bit.ACQPS  = acqps; //sample is acqps + 1 SYSCLK cycles
    AdcaRegs.ADCSOC3CTL.bit.ACQPS  = acqps; //sample is acqps + 1 SYSCLK cycles
    AdcaRegs.ADCSOC4CTL.bit.ACQPS  = acqps; //sample is acqps + 1 SYSCLK cycles
    AdcaRegs.ADCSOC5CTL.bit.ACQPS  = acqps; //sample is acqps + 1 SYSCLK cycles

    AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT1 flag
    AdcaRegs.ADCINTSEL1N2.bit.INT2E = 1; //enable INT2 flag
    AdcaRegs.ADCINTSEL3N4.bit.INT3E = 0; //disable INT3 flag
    AdcaRegs.ADCINTSEL3N4.bit.INT4E = 0; //disable INT4 flag

    AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 2;  //end of SOC2 will set INT1 flag
    AdcaRegs.ADCINTSEL1N2.bit.INT2SEL = 4; //end of SOC4 will set INT2 flag

    AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared
    AdcaRegs.ADCINTFLGCLR.bit.ADCINT2 = 1; //make sure INT2 flag is cleared
    //
    // Trigger source
    //
    AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 5; //ePWM1, ADCSOCA
    AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 5; //ePWM1, ADCSOCA
    AdcaRegs.ADCSOC2CTL.bit.TRIGSEL = 5; //ePWM1, ADCSOCA
    AdcaRegs.ADCSOC3CTL.bit.TRIGSEL = 5; //ePWM1, ADCSOCA
    AdcaRegs.ADCSOC4CTL.bit.TRIGSEL = 5; //ePWM1, ADCSOCA
    AdcaRegs.ADCSOC5CTL.bit.TRIGSEL = 5; //ePWM1, ADCSOCA

    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;      // Stop all the TB clocks

    // The clock source of EPWM is EPWMCLK

    /*-------------------------------------------------------------------------------------------------------------------------*/
     //The setting of EPWM1
     EPwm1Regs.TBSTS.all=0;
     EPwm1Regs.TBPHS.bit.TBPHS=0;
     EPwm1Regs.TBCTR=0;
     EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module, don't load the TBCTR from TBPHS
     EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;  // sync flow-through

     EPwm1Regs.CMPCTL.all=0;                 //Set the control register of Counter compare module
                                             //Counter compare B- in shadow mode
                                             //Counter compare A- in shadow mode
                                             //Load compare register B at TBCTR = 0x0000
                                             //Load compare register A at TBCTR = 0x0000
     //EPwm1Regs.CMPCTL.all=0x05;                    //Set the control register of Counter compare module
                                             //Counter compare B- in shadow mode
                                             //Counter compare A- in shadow mode
                                             //Load compare register B at TBCTR = PRD
                                             //Load compare register A at TBCTR = PRD

     EPwm1Regs.CMPA.bit.CMPA = 0;           //Clear compare register A & B
     EPwm1Regs.CMPB.bit.CMPB = 0;
     EPwm1Regs.AQCTLA.all=0x90;             // 0b10010000,
                                            // EPWMxA = 0 when CTR=CMPA and counter inc
                                            // EPWMxA = 1 when CTR=CMPA and counter dec
     EPwm1Regs.AQCTLB.all=0x900;            // 0b100100000000
                                            // EPWMxB = 0 when CTR=CMPB and counter inc
                                            // EPWMxB = 1 when CTR=CMPB and counter dec
     EPwm1Regs.AQSFRC.all=0;
     EPwm1Regs.AQCSFRC.all=0;
     //EPwm1Regs.DBCTL.all=0;

     //DB clocked at TBCLK default
     EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; //Deadtime enable for EPWMA and EPWMB
     EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;      //EPWMxB is inverted, complementary output
     EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;         //The EPWMxA is selected as the only source
     EPwm1Regs.DBCTL.bit.SHDWDBFEDMODE = 1;         //1: FED Shadow Mode
     EPwm1Regs.DBCTL.bit.SHDWDBREDMODE = 1;         //1: RED Shadow Mode
     EPwm1Regs.DBFED.bit.DBFED = 10;                          // Setting deadtime 10ns*10, = 100ns
     EPwm1Regs.DBRED.bit.DBRED = 10;

     EPwm1Regs.ETSEL.all=0;            // Interrupt disable
     EPwm1Regs.ETFLG.all=0;
     EPwm1Regs.ETCLR.all=0;
     EPwm1Regs.ETFRC.all=0;

     // SOCA for
     EPwm1Regs.ETSEL.bit.SOCAEN = 1;                 // Enable SOCA to trigger Seq1
     EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO;      // SOCA at zero
     EPwm1Regs.ETPS.bit.SOCAPRD = ET_1ST;             // Generate SOCA every event
     // SOCB for
     //EPwm1Regs.ETSEL.bit.SOCBEN = 1;                 // Enable SOCB to trigger Seq1
     //EPwm1Regs.ETSEL.bit.SOCBSEL = ET_CTR_PRD;       // SOCB at PRD
     //EPwm1Regs.ETPS.bit.SOCBPRD = ET_1ST;            // Generate SOCB every event

     EPwm1Regs.PCCTL.all = 0;

     EPwm1Regs.TBCTL.all = 0x201A;
                                                 // Count up after synchronization event
                                                 // Set Time base control register, TBCLK = EPWMCLK
                                                 // Select the CTR = zero as the TB_SYNC_OUT
                                                 // the shadow register of PRD disabled,immediately load
                                                 //
                                                 // up-down-count mode
     EPwm1Regs.TBPRD=SP;                         // load PRD register, PWM_CLK/(2*PWM_Freq)
     EDIS;

        EALLOW;
        PieCtrlRegs.PIECTRL.bit.ENPIE = 1;

        PieVectTable.ADCA1_INT = &Control_isr;
        EDIS;
        PieCtrlRegs.PIEIER1.bit.INTx1 = 1;

        IER |= M_INT1; //Enable group 1 interrupts
//
// Enable global Interrupts and higher priority real-time debug events:
//
        EINT;  // Enable Global interrupt INTM
        ERTM;  // Enable Global real time interrupt DBGM

ADC_ISR Code:

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interrupt void Control_isr(void)
{
    nCnt_INT_Idts++;
    // Read ADC Results
    ...
    // End reading
    
    
    AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
    PieCtrlRegs.PIEACK.bit.ACK1 = 1; //Acknowledge group 1 interrupt
}
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interrupt void Control_isr(void)
{

    nCnt_INT_Idts++;
    // Read ADC Results
    ...
    // End reading
    
    
    AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
    PieCtrlRegs.PIEACK.bit.ACK1 = 1; //Acknowledge group 1 interrupt

}

Is there any problem?

over 2 years ago

0 MatthewPate over 2 years ago

TI__Guru* 77720 points

Can you clear the INT at the beginning of the ISR vs at the end? My only concern is if the ISR is quite long, you could get another ADC ISR before the flag is cleared, which would result in missing the new ISR/flag getting set. I don;t think this would hang, since the next ISR should happen after the flag is cleared, but that could explain missing an ISR.

Best,
Matthew

0 Alvin over 2 years ago in reply to MatthewPate

Prodigy 130 points

Hi Matthew,

The ADC ISR will not be triggered in my case, not missing an ISR. And main loop is working normally.

BR/Alvin

0 MatthewPate over 2 years ago in reply to Alvin

TI__Guru* 77720 points

Alvin,

To clarify, when the issue happens you don't get any ADC ISRs at all from time =0. Only way to recover is to re-start/reboot?

I'd like you to set the INT1CONT bit located in the ADCINTSEL1N2 register as part of your ADC setup. This will eliminate the need for clearing the ADCINTFLG to get future ISRs(you can leave that line in your ISR, it won't have a negative effect). If this works, then there is likely a code ordering issue with enabling the ISR/INT and the ADC interrupt coming. If that first ADCINT is missed I can see how no others will get triggered/interrupted.

Best,

Matthew

0 Alvin over 2 years ago in reply to MatthewPate

Prodigy 130 points

Hi Matthew,

No, The ADC ISRs running 28543 cycle, nCnt_INT_Idts is 28543 and will not be increased forever, that is ADC ISRs can not be entered, Only way to recover is to re-start, i haven't try a reboot. By the way, what is the reboot instruction?

I will try to set the INT1CONT bit to see if it is useful.

BR/Alvin

0 MatthewPate over 2 years ago in reply to Alvin

TI__Guru* 77720 points

I was using re-start/reboot interchangably here, if you had programmed your code into flash and were running standalone I was meaning that to get out of the case you had to assert XRSn, etc.

For now let's focus on with CCS attached and using Restart. Will look for your update on INT1CONT option.

Best,
Matthew

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TMS320F28377D: ADC ISR ADCA1_INT Cannot be Triggered after 28543 cycle