TIDM-1010: BiSS-C library usage of EPWMs and Clocks

Jennifer Stander said:

1) In the example design in PM_bissc_setupPeriph EPWM1A is connected to CLB_IN0,6 and 7 of CLB3 and CLB4. In the example EPWM1 is never configured. What is the intended behavior of this signal? What does it do?

None of the PWMS are used as an input for this design. If it is connected to the tile, that input isn't connected to anything within the tile.  The EPWM4 is used by the CLB as a route to a pin - that is it overrides the PWM output functionality in order to get a signal from the CLB to a pin.  

Jennifer Stander said:

2) In the example design in PM_bissc_configureCLBLength CLB_ADDR_COUNTER_1_MATCH1 in CLB4_BASE is forced to 200. What is this value? If the CLB is clocked at 100MHz should this change to 100?

Offhand I don't know what the counter1 match1 is used for and would need some time to dig into it. Unfortunately we do not have documentation that clearly details the CLB implementation of this design. 

Jennifer Stander said:

3) When we pass 25 into PM_bissc_setFreq we get a 4 MHz BiSS-C output clock, the documentation and comments indicate that this should be 2 MHz. clock frequency = SYSCLK/(4*BISSC_FREQ_DIVIDER). Our SYSCLK is 200 MHz, seems like we are now off by a factor of 2?

The comment is incorrect. It is a scaling from the CLB clock itself to the BISS clk, not from SYSCLK. The CLB on F2837xD that the library is provided for also runs at 100MHz so the scaling doesn't need to be changed. 

Jennifer Stander said:

4) I am sure this is a stupid question, Clock is clearly coming out on the correct pins and the pins are configured to connect to EPWM4A and 4B. When we set things up we use the trip zone to force the outputs high but I don't understand in the code how the CLB talks to the EPWM. The EPWM4 is enabled but other than the tripzones is not configured. How does the CLB control the EPWM? How do they physically connect, i.e. what CLB outputs connect to EPWM inputs?

The CLB is overriding the ePWM4 functionality to reach these pins. The CLB bring some peripheral signals in and can also override some signals as an output. It is possible to customize some peripherals using the CLB.

Thank you for your quick and helpful response

1) In the example design in PM_bissc_setupPeriph EPWM1A is connected to CLB_IN0,6 and 7 of CLB3 and CLB4. In the example EPWM1 is never configured. What is the intended behavior of this signal? What does it do?

Lori Response

None of the PWMS are used as an input for this design. If it is connected to the tile, that input isn't connected to anything within the tile.  The EPWM4 is used by the CLB as a route to a pin - that is it overrides the PWM output functionality in order to get a signal from the CLB to a pin. 

Jennifer reply

We generated a block diagram of the CLB logic.Tile4 in0 and in7 and Tile in0 feed into CLB logic and level of input affects the behavior. What should we do with this signal? Should we tie it high or low?

What CLB output connects to the BISS clock?
What CLB output connects to the SPI clock?

3) When we pass 25 into PM_bissc_setFreq we get a 4 MHz BiSS-C output clock, the documentation and comments indicate that this should be 2 MHz. clock frequency = SYSCLK/(4*BISSC_FREQ_DIVIDER). Our SYSCLK is 200 MHz, seems like we are now off by a factor of 2?

             The comment is incorrect. It is a scaling from the CLB clock itself to the BISS clk, not from SYSCLK. The CLB on F2837xD that the library is provided for also runs at 100MHz so the scaling doesn't need to be changed. 

              Jennifer Reply

              If I am running at 100 MHz with a BISSC_FREQ_DIVIDER of 25. clock frequency = CLB_CLK/(2*BISSC_FREQ_DIVIDER). The expected value is 2 MHz not 4 MHz? If we are getting 4 MHz that would imply our CLB clock is running at 200 MHz?

Jennifer Stander said:

We generated a block diagram of the CLB logic.Tile4 in0 and in7 and Tile in0 feed into CLB logic and level of input affects the behavior. What should we do with this signal? Should we tie it high or low?

If it is used it is not ePWM. The inputs will be GPREG for the C28x, MA from the encoder through the CLB MUX, or a connection from another tile. Since we don't have this documented well, I will have to look into this. I am out of office until next Wednesday so there will be a delay. 

Jennifer Stander said:

What CLB output connects to the BISS clock?
What CLB output connects to the SPI clock?

Since it is overriding ePWM4 it is probably Tile4 output 0. The outputs and what they can connect to is documented in the CLB portion of the TRM. The output coming through the XBAR will be TILE x - either output 4 or 5 since those connect to xbars on F2837xD.

Jennifer Stander said:

    If I am running at 100 MHz with a BISSC_FREQ_DIVIDER of 25. clock frequency = CLB_CLK/(2*BISSC_FREQ_DIVIDER). The expected value is 2 MHz not 4 MHz? If we are getting 4 MHz that would imply our CLB clock is running at 200 MHz?

The scale factor changes a counter match value to determine the edges (i.e. the width) of the BiSS clock. That is it is a ratio of how many CLB clocks fit into the time low or time high of the BiSS clock. For a given CLB clock and BiSS clock, it will always be the same ratio. 

Thank you for your help and will await further responses next week to confirm signal functionality.