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TMS320F2800137: UART RXSHF -> SCIRXBUF condition

HS FAE Germany
Mastermind 31670 points
Part Number: TMS320F2800137

Hi,
I have some general questions.

The data will only transfered from RXSHF to SCIXBUF if no receive error RXERROR (bits 5-2: BRKDT, FE, OE, and PE) occurs, ok?

RXSHF begin receiving with the start bit? What is the condition to detect a start bit? Long time high (how many SCICLK???) followed by by four consecutive
internal SCICLK periods of zero bits.

After an detected error the RXSHF will be cleared? At each new start bit the RXSHF will be cleared?

Two bit error can't be detected, right?

Regards, Holger

  • 0
    TI__Mastermind 19795 points

    Hi Holger,

    HS FAE Germany said:
    RXSHF begin receiving with the start bit? What is the condition to detect a start bit? Long time high (how many SCICLK???) followed by by four consecutive
    internal SCICLK periods of zero bits.

    This is mentioned in the SCI TRM Chapter:

    All other items are mentioned in the various register descriptions of each of the items you mentioned. If you have questions on specific wordings in the TRM registers, please let me know, and provide screenshots of what you have confusion on.

    Regards,

    Vince

  • 0 in reply to Vince
    TI__Mastermind 31670 points

    it would be easier you had quickly answered my questions instead of the hint RTFM

  • +1 in reply to HS FAE Germany
    TI__Mastermind 19795 points

    My apologies, did not mean for it to come across that way.

    Here are the direct answers to your questions:

    HS FAE Germany said:
    The data will only transfered from RXSHF to SCIXBUF if no receive error RXERROR (bits 5-2: BRKDT, FE, OE, and PE) occurs, ok?

    Yes, however data should transfer regardless into RXSHF FROM PIN unless there is something disabling the RXENA bit.

    HS FAE Germany said:
    RXSHF begin receiving with the start bit? What is the condition to detect a start bit? Long time high (how many SCICLK???) followed by by four consecutive
    internal SCICLK periods of zero bits.

    Yes. Condition is 4 low SCICLK periods. The high period does not matter in this case as long as it is greater than 1 bit. 2 stop bits of high is recommended.

    HS FAE Germany said:
    After an detected error the RXSHF will be cleared? At each new start bit the RXSHF will be cleared?

    Other than new start bit, RXSHF will not get cleared unless SCI reset occurs, or the data is shifted into the fifo/buffer. RXSHF clears on new start bit.

    HS FAE Germany said:
    Two bit error can't be detected, right?

    Correct.

  • 0 in reply to Vince
    TI__Mastermind 31670 points

    thanks, Vince.