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TMS320F280049: How to clear SCIRXBUF

Sh.Sasaki
Guru 13625 points

Part Number: TMS320F280049

Hi experts,

Is there any way to clear SCIRXBUF other than a system reset?

The TRM includes the following description. However, our customers want to clear the SCIFFFE and SCIFFPE bits in this register in software.

My customers can't shut down the system, so they want to reset only SCI, not the system reset.

Is there any way to accomplish this?

Best regards,

Sasaki

  • 0
    TI__Mastermind 19795 points

    Hello Sasaki,

    Thank you for your question. These bits (SCIFFFE and SCIFFPE) are only cleared by system reset. Please see the following threads regarding this:

    https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/903529

    https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/901500?TMS320F280049C-SCI-channel-reset-clarifications

    Please see the sections in the above threads about clearing the other error flags (using SWRESET bit).

    Regards,

    Vince

    ----------------------------------------------------------------------------------------------------------------------------

    If I was able to answer your question, please press the green "Verified" button below, thanks!

  • 0 in reply to Vince
    Guru 13625 points

    Hello Vince-san,

    Thank you for your reply.

    Vince Toledo said:
    Thank you for your question. These bits (SCIFFFE and SCIFFPE) are only cleared by system reset. Please see the following threads regarding this:

    Does this mean that the device should do a system reset every time it gets a parity error in FIFO mode?

    If the above is correct, I don't think it is practical to use SCI in FIFO mode.

    Best regards,
    Sasaki

  • 0 in reply to Sh.Sasaki
    TI__Mastermind 19795 points

    Hi Sasaki-san,

    I am currently following up with our internal team to determine if there is another method to do this. I will update once they get back with information.

    Regards,

    Vince

    ----------------------------------------------------------------------------------------------------------------------------

    If I was able to answer your question, please press the green "Verified" button below, thanks!

  • 0 in reply to Vince
    Guru 13625 points

    Hi Vince-san,

    Thanks for your reply.

    Do you have any update?

    Best regatds,
    Sasaki

  • 0 in reply to Sh.Sasaki
    TI__Mastermind 19795 points

    Hi Sasaki,

    Thanks for checking in. We are now in the testing phase of a potential sequence for this request. I will give you an update on this by Thursday of this week. Thank you for your time.

    Regards,

    Vince

  • 0 in reply to Vince
    TI__Mastermind 19795 points

    Hi Sasaki,

    Thank you for your patience on this. We were able to test the following sequence and determine its validity on hardware. This allows clearing of the bits discussed previously. Please let me know if you have any questions!

    SCIFFFE or SCIFFPE set, begin sequence:

    1. Read 16 times from RXBUF_SAR_M (to clear entire FIFO)
    2. FIFO mode disable
    3. FIFO mode enable
    4. Loopback enable (dummy internal loopback transaction will clear the SCIFFFE/SCIFFPE status)
    5. Write to TXBUF until FFTX_TXFFST status reaches 16 words (to clear entire TX FIFO)
    6. While TX FIFO not empty (TXFFST == 0 words), wait (for TX FIFO to empty)
    7. While RX FIFO not empty (RXFFST != 0), read RXBUF_SAR and discard data (clears RX FIFO)
    8. Loopback disable
    9. SWRESET assert/de-assert
    10. TX/RXFIFORESET assert/de-assert

    Regards!

    Vince

  • 0 in reply to Vince
    Guru 13625 points

    Hi Vince-san,

    Thank you for your special support!!

    We will contact my customer with this information.

    Best regards,
    Sasaki