TMS320F28386D: Data width different between C28X and CLA core

typedef struct
{
Uint32_t u32Base;
ADC_ClkPrescale eClkPrescale;
ADC_Resolution eResolution;
ADC_SignalMode eSignalMode;
ADC_PulseMode ePulseMode;
ADC_IntNumber eAdcIntNum;
ADC_SOCNumber eSocNumber;
}DrvAdcConfig_t;

typedef enum
{
ADC_CLK_DIV_1_0 = 0, //!< ADCCLK = (input clock) / 1.0
ADC_CLK_DIV_2_0 = 2, //!< ADCCLK = (input clock) / 2.0
ADC_CLK_DIV_2_5 = 3, //!< ADCCLK = (input clock) / 2.5
ADC_CLK_DIV_3_0 = 4, //!< ADCCLK = (input clock) / 3.0
ADC_CLK_DIV_3_5 = 5, //!< ADCCLK = (input clock) / 3.5
ADC_CLK_DIV_4_0 = 6, //!< ADCCLK = (input clock) / 4.0
ADC_CLK_DIV_4_5 = 7, //!< ADCCLK = (input clock) / 4.5
ADC_CLK_DIV_5_0 = 8, //!< ADCCLK = (input clock) / 5.0
ADC_CLK_DIV_5_5 = 9, //!< ADCCLK = (input clock) / 5.5
ADC_CLK_DIV_6_0 = 10, //!< ADCCLK = (input clock) / 6.0
ADC_CLK_DIV_6_5 = 11, //!< ADCCLK = (input clock) / 6.5
ADC_CLK_DIV_7_0 = 12, //!< ADCCLK = (input clock) / 7.0
ADC_CLK_DIV_7_5 = 13, //!< ADCCLK = (input clock) / 7.5
ADC_CLK_DIV_8_0 = 14, //!< ADCCLK = (input clock) / 8.0
ADC_CLK_DIV_8_5 = 15 //!< ADCCLK = (input clock) / 8.5
} ADC_ClkPrescale;

In C28X, When creat the instace of DrvAdcConfig_t, the C28x core will treat the element .eClkPrescale as 16bits.

But when want use this element in the CLA, find that .eClkPrescale is32 bits, and face the Address alignment issue