TMS320F28379D: ISR overruns when ran from Flash instead of RAM

Sanjay Kannan

Part Number: TMS320F28379D

Hello,

I have a code that is running inside ADC ISR (interrupts every 20 us). It is running without any issues when ran from RAM, whereas there is an ISR overrun when it is run from flash (The code inside the ISR seems to take more than 20 us)

I checked the wait-state configuration inside the InitFlash() function (In the SysCtrl.c file). The RWAIT bit is set to 0x3 for a CPU frequency of 200MHz, which is our operating CPU frequency. The datasheet also says that the minimum wait-states need to be 0x3 for 200MHz clock.

Are any other changes that can be made to the configuration such that it doesn't lead to an ISR overrun?

Thanks.

over 1 year ago

0 Sinchita Maity over 1 year ago

TI__Prodigy 680 points

Hello,

Due to US holiday please expect response by 20th February.

Thanks & Regards,

Sinchita

0 MatthewPate over 1 year ago in reply to Sinchita Maity

TI__Guru* 80250 points

Sanjay,

Could you share your linker(.cmd) file for the RAM and Flash use case? I think that will help narrow down any potential issue.

Best,
Matthew

0 Sanjay Kannan over 1 year ago in reply to MatthewPate

Prodigy 10 points

Fullscreen RAM linker.txt Download

MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */

   BEGIN           	: origin = 0x000000, length = 0x000002
   RAMM0           	: origin = 0x000122, length = 0x0002DE
   RAMD0           	: origin = 0x00B000, length = 0x000800
   RAMLS0          	: origin = 0x008000, length = 0x002000
 //  RAMLS1          	: origin = 0x008800, length = 0x000800
  // RAMLS2      		: origin = 0x009000, length = 0x000800
  // RAMLS3      		: origin = 0x009800, length = 0x000800
   RAMLS4      		: origin = 0x00A000, length = 0x001000
   RESET           	: origin = 0x3FFFC0, length = 0x000002



PAGE 1 :

   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAMD1           : origin = 0x00B800, length = 0x000800


  // RAMLS5      : origin = 0x00A800, length = 0x000800

	RAMGS0       : origin = 0x00C000, length = 0x004000
   //RAMGS0      : origin = 0x00C000, length = 0x001000
   RAMGS1      : origin = 0x010000, length = 0x001000
//   RAMGS2      : origin = 0x00E000, length = 0x001000
 //  RAMGS3      : origin = 0x00F000, length = 0x001000
//   RAMGS4      : origin = 0x010000, length = 0x001000
   RAMGS5      : origin = 0x011000, length = 0x00B000
  //RAMGS6      : origin = 0x012000, length = 0x001000
   //RAMGS7      : origin = 0x013000, length = 0x001000
   //RAMGS8      : origin = 0x014000, length = 0x001000
   //RAMGS9      : origin = 0x015000, length = 0x001000
   //RAMGS10     : origin = 0x016000, length = 0x001000
   //RAMGS11     : origin = 0x017000, length = 0x001000
   //RAMGS12     : origin = 0x018000, length = 0x001000

//   RAMGS13     : origin = 0x019000, length = 0x001000
//   RAMGS14     : origin = 0x01A000, length = 0x001000
  // RAMGS15     : origin = 0x01B000, length = 0x001000
     //RAMGS15    		: origin = 0x019000, length = 0x003000
   
   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
}
SECTIONS
{
   codestart        : > BEGIN,     PAGE = 0
   
#ifdef __TI_COMPILER_VERSION__
   #if __TI_COMPILER_VERSION__ >= 15009000
    .TI.ramfunc : {} > RAMM0,      PAGE = 0
   #else
   ramfuncs         : > RAMM0      PAGE = 0   
   #endif
#endif   
   
   //.text            : >>RAMM0 | RAMD0 |  RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4 | RAMGS15,   PAGE = 0
   .text            : >>RAMM0 | RAMD0 |  RAMLS0 , PAGE = 0
   .cinit           : > RAMM0 | RAMLS4,     PAGE = 0
   .pinit           : > RAMM0,     PAGE = 0
   .switch          : > RAMM0,     PAGE = 0
   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */

   .stack           : > RAMM1,     PAGE = 1
   .ebss            : > RAMGS5 | RAMGS1 | RAMGS0,     PAGE = 1			//changed from RAMLS5
   .econst          : > RAMLS4,    PAGE = 0			//changed from RAMLS5
   .esysmem         : > RAMGS5,    PAGE = 1			//changed from RAMLS5
   Filter_RegsFile  : > RAMGS0,	   PAGE = 1

   ramgs0           : > RAMGS0,    PAGE = 1
   ramgs1           : > RAMGS1,    PAGE = 1
   
   /* The following section definitions are required when using the IPC API Drivers */ 
    GROUP : > CPU1TOCPU2RAM, PAGE = 1 
    {
        PUTBUFFER 
        PUTWRITEIDX 
        GETREADIDX 
    }
    
    GROUP : > CPU2TOCPU1RAM, PAGE = 1
    {
        GETBUFFER :    TYPE = DSECT
        GETWRITEIDX :  TYPE = DSECT
        PUTREADIDX :   TYPE = DSECT
    }  
	
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Fullscreen Flash linker.txt Download

MEMORY
{
PAGE 0 :  /* Program Memory */
          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
          /* BEGIN is used for the "boot to Flash" bootloader mode   */

   BEGIN           	: origin = 0x080000, length = 0x000002
   RAMM0           	: origin = 0x000122, length = 0x0002DE
   RAMD0           	: origin = 0x00B000, length = 0x000800
   RAMLS0          	: origin = 0x008000, length = 0x000800
   RAMLS1          	: origin = 0x008800, length = 0x000800
   RAMLS2      		: origin = 0x009000, length = 0x000800
   RAMLS3      		: origin = 0x009800, length = 0x000800
   RAMLS4      		: origin = 0x00A000, length = 0x000800
   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS15          : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RESET           	: origin = 0x3FFFC0, length = 0x000002

   /* Flash sectors */
   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */

PAGE 1 : /* Data Memory */
         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */

   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAMD1           : origin = 0x00B800, length = 0x000800

   RAMLS5      : origin = 0x00A800, length = 0x000800

   RAMGS0       : origin = 0x00C000, length = 0x004000
      //RAMGS0      : origin = 0x00C000, length = 0x001000
      RAMGS1      : origin = 0x010000, length = 0x001000
   //   RAMGS2      : origin = 0x00E000, length = 0x001000
    //  RAMGS3      : origin = 0x00F000, length = 0x001000
   //   RAMGS4      : origin = 0x010000, length = 0x001000
      RAMGS5      : origin = 0x011000, length = 0x00B000
//   RAMGS0      : origin = 0x00C000, length = 0x001000
//   RAMGS1      : origin = 0x00D000, length = 0x001000
//   RAMGS2      : origin = 0x00E000, length = 0x001000
//   RAMGS3      : origin = 0x00F000, length = 0x001000
//   RAMGS4      : origin = 0x010000, length = 0x001000
//   RAMGS5      : origin = 0x011000, length = 0x001000
//   RAMGS6      : origin = 0x012000, length = 0x001000
//   RAMGS7      : origin = 0x013000, length = 0x001000
//   RAMGS8      : origin = 0x014000, length = 0x001000
//   RAMGS9      : origin = 0x015000, length = 0x001000
//   RAMGS10     : origin = 0x016000, length = 0x001000
//   RAMGS11     : origin = 0x017000, length = 0x001000
//   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
//   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
}

SECTIONS
{
   /* Allocate program areas: */
   .cinit              : > FLASHB      PAGE = 0, ALIGN(4)
   .pinit              : > FLASHB,     PAGE = 0, ALIGN(4)
   .text               : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(4)
   codestart           : > BEGIN       PAGE = 0, ALIGN(4)

   /* Allocate uninitalized data sections: */
   .stack              : > RAMM1        PAGE = 1
   .ebss            : > RAMGS5 | RAMGS1 | RAMGS0     PAGE = 1          //changed from RAMLS5
   //.ebss               : >> RAMLS5 | RAMGS0 | RAMGS1       PAGE = 1
   .esysmem            : > RAMLS5       PAGE = 1

   /* Initalized sections go in Flash */
   .econst             : >> FLASHF | FLASHG | FLASHH      PAGE = 0, ALIGN(4)
   .switch             : > FLASHB      PAGE = 0, ALIGN(4)

   .reset              : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */

   Filter_RegsFile     : > RAMGS0,	   PAGE = 1

   SHARERAMGS0		: > RAMGS0,		PAGE = 1
   SHARERAMGS1		: > RAMGS1,		PAGE = 1
   ramgs0           : > RAMGS0,     PAGE = 1
   ramgs1           : > RAMGS1,     PAGE = 1

#ifdef __TI_COMPILER_VERSION__
	#if __TI_COMPILER_VERSION__ >= 15009000
	.TI.ramfunc : {} LOAD = FLASHD,
						 RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         RUN_SIZE(_RamfuncsRunSize),
                         RUN_END(_RamfuncsRunEnd),
						 PAGE = 0, ALIGN(4)
	#else
   ramfuncs            : LOAD = FLASHD,
                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         RUN_SIZE(_RamfuncsRunSize),
                         RUN_END(_RamfuncsRunEnd),
                         PAGE = 0, ALIGN(4)
    #endif
#endif

   /* The following section definitions are required when using the IPC API Drivers */
    GROUP : > CPU1TOCPU2RAM, PAGE = 1
    {
        PUTBUFFER
        PUTWRITEIDX
        GETREADIDX
    }

    GROUP : > CPU2TOCPU1RAM, PAGE = 1
    {
        GETBUFFER :    TYPE = DSECT
        GETWRITEIDX :  TYPE = DSECT
        PUTREADIDX :   TYPE = DSECT
    }

   /* The following section definition are for SDFM examples */
//   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
//   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
//   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
//   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
//   Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Matthew,

I have attached the RAM and flash linker files with which I attempted running my code.

While running from Flash, I have the following lines of code in my code:

In the declarations:

extern unsigned int RamfuncsLoadStart;
extern unsigned int RamfuncsLoadEnd;
extern unsigned int RamfuncsRunStart;
extern void InitFlash(void);

and in void main(), after InitSysCtrl() is called, I have this:

memcpy(&RamfuncsRunStart,&RamfuncsLoadStart,&RamfuncsLoadEnd-&RamfuncsLoadStart);
InitFlash();

(I was unable to upload the .cmd files, so I copied them onto notepad, sorry for the messy reply!)

0 MatthewPate over 1 year ago in reply to Sanjay Kannan

TI__Guru* 80250 points

Sanjay,

Can you look in the file where InitFlash() function is defined(for me this is in F2837xD_SysCtrl.c) and make sure you see the following line near the top

#ifndef __cplusplus
    #ifdef __TI_COMPILER_VERSION__
        #if __TI_COMPILER_VERSION__ >= 15009000
            #pragma CODE_SECTION(InitFlash, ".TI.ramfunc");
            #pragma CODE_SECTION(FlashOff, ".TI.ramfunc");
        #else
            #pragma CODE_SECTION(InitFlash, "ramfuncs");
            #pragma CODE_SECTION(FlashOff, "ramfuncs");
        #endif
    #endif
#endif

This is what tells the linker that InitFlashI() is placed in the RAM section you have made.

Since we are also dealing with ADC ISR timing, you also need to add the ADC_ISR function(s) to the above CODE_SECTION pragmas, so those will also get loaded to flash but ran from RAM.

Let's see if the above helps, and we can go from there,

Best,

Matthew

0 Sanjay Kannan over 1 year ago in reply to MatthewPate

Prodigy 10 points

Matthew,

Yes, the SysCtrl.c file has the lines that you have shared.

Regarding adding the adc_isr function to the code_section pragmas,

Should it be done like this?

#pragma CODE_SECTION(adc_isr, ".TI.ramfunc");

Thanks,

Sanjay

0 MatthewPate over 1 year ago in reply to Sanjay Kannan

TI__Guru* 80250 points

Yes, it should just be the function name.

Can you also send(or C/P) the contents of the .map file that gets generated for each build? It will be in the same directory as your .out file or one dir up. It is just a plain text file that shows where all memory is getting allocated.

Best,

Matthew

0 Sanjay Kannan over 1 year ago in reply to MatthewPate

Prodigy 10 points

/cfs-file/__key/communityserver-discussions-components-files/171/modifiedlinker.txt

/cfs-file/__key/communityserver-discussions-components-files/171/5584.MAP-file.txt

Matthew,

I added the adc_isr function to the CODE_SECTION pragma. Initially I got an error, but I was able to resolve it by making RAMLS0 as one contiguous memory where the entire code could fit, and it built without issues.

I have attached the .map file for this build, as well the modified flash linker file that I used.

Also, I set a GPIO at the start and cleared it at the end of the adc_isr function to see how long it takes, and it is within 20us compared to the earlier case where it quit the ISR. Thanks for the help!

Are there any other ways to optimize this further?

0 MatthewPate over 1 year ago in reply to Sanjay Kannan

TI__Guru* 80250 points

Sanjay,

I haven't looked at the files yet, but some ideas on decreasing the time:

1)Optimization level; right click on your .pjt and then select "properties" at the bottom. This will bring up a new dialogue, go to Buiild->C2000 Compiler -> Optimization. We typically recommend opt level 2/Global Optimizations. You can try different slider option for speed/size tradeoffs, but we usually start with 2(which should be the default). After you change this and Apply, you'll need to re-build the project to realize the improvements.

1a)You'll also notice that floating point mode drop down. If you have floating point operations in your ISR(or just code) you can set this to "relaxed" which will use the some optimized HW/SW routines to speed that up. The difference is that "relaxed" mode does not strictly adhere to the ANSI C requirements for floating point operations. You can read more about this here https://www.ti.com/lit/spry288

2)Code debug checks. There is by default, many checks in the drivers for correct arguments and error handlers if there is some invalid options passed. If your code is running correctly you can remove these(usually done before release). In that same dialogue window we had open, go to "predefined symbols" still under C2000 Compiler. Remove the DEBUG predefine from this list, and re-compile. You should notice some improved performance here as well.

I'll take a look at your maps, sometimes there are memory conflicts between program execution and data storage that can slow things down as well.

Best,

Matthew

0 Sanjay Kannan over 1 year ago in reply to MatthewPate

Prodigy 10 points

Matthew,

Thanks for the suggestions. I have incorporated them in my code. Did you find any issues with the maps?

+1 MatthewPate over 1 year ago in reply to Sanjay Kannan

TI__Guru* 80250 points

Sanjay,

I believe things look good now, there doesn't appear to be any memory conflicts that would slow things down due to arbitration. One last thing, I see that RAMGS0 and RAMGS1 are defined twice

SHARERAMGS0 : > RAMGS0, PAGE = 1
SHARERAMGS1 : > RAMGS1, PAGE = 1
ramgs0 : > RAMGS0, PAGE = 1
ramgs1 : > RAMGS1, PAGE = 1

You can check your main code, to see if these are referenced for run time use(like a buffer), just wanted to make sure we are not using twice with different names. I think this would show up in the map, and I didn't see anything in those ranges at first pass, but thought I'd mention it.

Best,

Matthew

0 Sanjay Kannan over 1 year ago in reply to MatthewPate

Prodigy 10 points

Matthew,

Thanks for all the help!

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TMS320F28379D: ISR overruns when ran from Flash instead of RAM